8 chapter 7

Chapter 7 Introduction to FETs Field-effect transistors (FETs) are unipolar devices, because unlike BJTs that use both electron and hole current, they operate only with one type of charge carrier. The two main types of FETs are the junction field-effect transistor (JFET) and the metal oxide semiconductor field-effect transistor (MOSFET). A BJT is a currentcontrolled device; that is, the base current controls the amount of collector currents. A FET is different. It is a voltage-controlled device, where the voltage between two of the terminals (gate and source) controls the current through the device.

JFET [5] Basic Structure: The JFET (junction field-effect transistor) is a type of FET that operates with a reverse-biased pn junction to control the current in a channel. There are two types of the channel, n channel and p channel. Figure 7.1 (a) shows the basic structure of an n-channel JFET. Wire leads called the drain is connected to the upper end and wire leads, called the source is connected to the lower end of the nchannel. Two p-type regions are used to formed a channel, and both p-type regions 272 | P a g e

are connected to the gate lead. For simplicity, the gate lead is shown connected to only one of the p regions. A p-channel JFET is shown in figure 7.1(b).

Figure 7.1 A representation of the basic structure of the two types of JFET. [5]

Basic Operation: Figure 7.2 shows dc bias voltages applied to an n-channel JFET. VDD provides a drain-to-source voltage and supplies current from drain to source. V GG sets the reverse-bias voltage between the gate and the source. The JFET is always operated with the gate-source pn junction reverse-biased. Reverse-biasing of the gate-source junction with a negative gate voltage produces a depletion region along the pn junction, which extends into the n channel and thus increases its resistance by decreasing the channel width. The channel width and the channel resistance can be controlled by varying the gate voltage, thereby controlling the amount of drain current ID. Figure 7.3 illustrates this concept when VGG = VGS.

Figure 7.2 A biased n-channel JFET. [5] 273 | P a g e

Figure 7.3 Effects of VGS on channel width, resistance, and drain current. [5] JFET symbols: The schematic symbols for both n-channel and p-channel JFETs are shown in figure 7.4. Notice that the arrow on the gate points “in” for n channel and “out” for p channel.

Figure 7.4 JFET symbols. [5] 274 | P a g e

JFET CHARACTERISTICS AND PARAMETERS [5] Drain Characteristic Curve: Consider the case when the gate-to-source voltage is zero (VGS = 0 V). This is produced by shorting the gate to the source, as in Figure 7.5 (a). As VDD is increased from 0 A, ID will increase proportionally, as shown in Figure 7.5 (b) between point A and B. In this area, the channel resistance is essentially constant because the depletion region is not large enough to have significant effect. This is called the ohmic area because VDS and ID are related by Ohm’s law. At point B in Figure 7.5 (b), ID becomes essentially constant. As VDS increases from point B to point C, the reverse-bias voltage from gate to drain (VGD) produces a depletion region large enough to offset the increase in VDS, thus keeping ID relatively constant. For VGS = 0 V, the value of VDS at which ID becomes constant (point B on the curve in Figure 7.5 (b) is the pinch-off voltage, VP. Above the pinch-off voltage, ID is almost constant. This value of drain current is IDSS (Drain to source current with gate shorted) and is always specified on JFET data sheets, and it is always specified for the condition, VGS = 0 V. As shown in Figure 7.5(b), breakdown occurs at point C when ID begins to increase vary rapidly with any further increase in VDS. Breakdown can result in damage to the device, So JFETs are operated below breakdown and within the constant-current area.

Figure 7.5 The drain characteristic curve of a JFET for VGS = 0 V. [5] 275 | P a g e

VGS controls ID: Let’s connect a bias voltage, VGG, from gate to source as shown in Figure 7.6 (a). As VGS is set to increasingly more negative values by adjusting V GG, a family of drain characteristics curves is shown in Figure 7.6 (b). Notice that ID decreases as the magnitude of VGS is increased to the larger negative values because of the narrowing of the channel. For each increase in negative values of VGS, the JFET reaches pinch-off at values of VDS less than VP. So, the amount of drain current is controlled by VGS.

Figure 7.6 Pinch-off occurs at a lower VDS as VGS is increased to more negative values. [5] Cutoff voltage: The value of VGS that makes ID approximately zero is the cutoff voltage, VGS(off). This cutoff effect is caused by the widening of the depletion region to a point where it completely closes the channel, as shown in figure 7.7. The JFET must be operated between VGS = 0 V and VGS(off). For this range of gate-to-source voltages, ID will vary from a maximum of IDSS to a minimum of almost zero. The relation between VP and VGS(off) is VP = –VGS(off).

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Figure 7.7 JFET at cutoff. [5] Example 1: (a) For the JFET, VGS(off) = – 4 V and IDSS = 12 mA. Determine the minimum value of VDD required to put the device in the constant-current are of operation.

Figure 7.8 For Example 1 [5] Solution:

Figure 7.9 For Example 1 277 | P a g e

(b) If VDD is increased to 15 V, what is ID and VDS? Solution: ID remains at approximately 12 mA.

Figure 7.10 For Example 1

JFET Transfer Characteristic: A range of VGS values from zero to VGS(off) controls the amount of drain current. For an n-channel JFET, VGS(off) is negative, and for a p-channel JFET, VGS(off) is positive. Because VGS does control ID, the relationship between these two quantities is very important. Figure 7.11 is a general transfer characteristic curve that illustrates graphically the relationship between VGS and ID. 278 | P a g e

Figure 7.11 JFET transfer characteristic curve (n-channel). [5] The JFET transfer characteristic curve shows that the operating limits of a JFET are ID = 0 when VGS = VGS(off) and

ID = IDSS

when VGS = 0

The JFET transfer characteristic curve can be developed from the drain characteristics curves, as illustrated in figure 7.12. For example, when V GS = – 2 V, ID = 4.32 mA. Also, for this specific JFET, VGS(off) = – 5 V, and IDSS = 12 mA.

Figure 7.12 n-channel JFET transfer characteristic curve (blue) from the JFET drain characteristic curves (green). [5] 279 | P a g e

A JFET transfer characteristic curve is expressed approximately as

Example 2: For a 2N5459 JFET, VGS(off) = – 8 V (maximum) and IDSS = 9 mA. Using these values, determine the drain current for VGS = 0 V, – 1 V, and – 4 V. Solution:

Example 3: 2N5457 JFET has values of VGS(off) = – 0.5 to – 6V and IDSS = 1 to 5 mA. Plot the minimum and maximum transconductance curves (or transfer characteristics) for the device. Solution:

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Using the minimum values of VGS(off) = – 0.5 V and IDSS = 1 mA, we can solve for the following points.

Figure 7.13 For Example 3

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JFET Biasing Circuits [5] 7.3.1 Gate Bias (or Fixed Bias) The gate bias of biasing arrangements for the n-channel JFET appears in Figure 7.14. The configuration of Figure 7.14 includes the ac levels Vi and Vo and the coupling capacitors (C1 and C2). Recall that the coupling capacitors are “open circuits” for the dc analysis and low impedances (essentially short circuits) for the ac analysis. The resistor RG is present to ensure that Vi appears at the input to the FET amplifier for the ac analysis.

Figure 7.14 Gated-bias configuration.

For the dc analysis,

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From Figure 7.15, using KVL:

Figure 7.15 Network for dc analysis.

Example 4: The JFET has values of VGS(off) = -8 V and IDSS = 16 mA. Determine the values of VGS, ID and VDS for the circuit.

Figure 7.16 For Example 4. 283 | P a g e

Solution:

Example 5: Determine the Q-point values for the gate biasing circuit if V GG = 0.5V , VGS(off) = -7 V , IDSS = 9 mA , VDD = 5 V and RD = 500 . Solution:

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Figure 7.17 For Example 5.

Example 6: From Figure 7.16, determine the range of Q-point values. Assume that the JFET has ranges of VGS (off) = – 1 to – 7 V and IDSS = 2 to 9 mA. Solution:

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Figure 7.18 For Example 6.

7.3.2 Self bias Self-bias is the most common type of JFET bias. Recall that a JFET must be operated such that the gate-source junction is always reverse-biased. This condition requires a negative VGS for an n-channel JFET and a positive VGS for a pchannel JFET. This can be achieved using the self-bias arrangements shown in Figure 7.19. The gate resistor, RG, does not affect the bias because it has essentially no voltage drop across it; and therefore the gate remains at 0 V.

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Figure 7.19 Self-bias configuration.

For the dc analysis,

Example 7: Determine the Q-point values for the self biasing circuit if V GS(off) = ‒ 8 V , IDSS = 16 mA , VDD = 10 V , RD = 500  , RG = 1 M and RS = 500 . Solution:

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Figure 7.20 For Example 7.

How to find Q-point??

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Example 8: Plot the range of Q-point values. Assume the JFET in the self biasing circuit has parameters of VGS(off) = -5 to -10 V and IDSS = 5 to 10 mA. Assume RD = 500  , RG = 1 M and RS = 500 . Solution:

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Figure 7.21 For Example 8.

7.3.3 Voltage-divider bias An n-channel JFET with voltage-divider bias is shown in Figure 7.22. The voltage at the source of the JFET must be more positive than the voltage at the gate in order to keep the gate-source junction reverse-biased.

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The method used to plot the dc bias line for the voltage-divider bias is as follows: 1. Plot the transconductance curve for the specific JFET. 2. Calculate VG. 3. Plot VG on the positive x-axis. V 4. Solve for ID using I D = G RS 5. Plot ID found in (4) on the y-axis. 6. Extend the line to intersect the transconductance curve to obtain the Qpoint values.

Example 9: Plot the dc bias line and the Q-point for the voltage-divider biasing circuit. Let R1 = 1.5 M, R2 = 1.5 M, RD = 1.1 k, RS = 10 k,VGS(off) = -8 V , IDSS = 16 mA and VDD = 30 V. Solution:

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For voltage – divider bias:

Figure 7.22 For Example 9.

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Example 10: Plot the dc bias line and the range of Q-point for the circuit shown in Figure 7.23. Here, assume VGS(off) = -2 to -8 V and IDSS = 4 to 16 mA.

Figure 7.23 For Example 10. Solution:

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For voltage – divider bias:

Figure 7.24 For Example 10.

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Homework 11 1. For the JFET in Figure 7.25, VGS(off) = 2 to 5 V and IDSS = 5 to 10 mA. (a) Using these values, plot the maximum transconductance curve, minimum transconductance curve, DC bias line and the range of Q-point values. (b) Determine the values of VGS and ID at the minimum Q-point.

Figure 7.25 For problem 1. 2. For this JFET, VGS(off) = 6 V and IDSS = 12 mA. (a) Using these values, plot the transconductance curve (or transfer characteristics), DC bias line and Q-point. (b) Determine the values of VGS and ID at Q-point.

Figure 7.26 For problem 2. 295 | P a g e

(a)

(b) Figure 7.27 For problem 3. 296 | P a g e

4. Consider the graph in Figure 7.28(a) and the circuit in Figure 7.28(b). (a) Find RS in the circuit of Figure 7.28(b). (b) Calculate the values of VGS and ID at the Qpoints in the graph in Figure 7.28(a). (c) Find RD in the circuit of Figure 7.28(b). ID (mA) 40

DC bias line

30

20 10 Q-point

VGS (V) - 20

- 15

- 10

-5

0

(a)

+ VDD + 20 V RD 1 k

+ 5V  R RGG 12 M M

RS

R S 1 k

(b)

Figure 7.28 For problem 4. 297 | P a g e

MOSFET [5] Recall that the reverse bias of the gate is varied to deplete the channel in JFETs. This type of operation is called depletion-mode operation. A depletion-type device is a device that uses an input voltage to reduce the size of the channel to control the amount of current. An enhancement-type device is a device that uses an input voltage to increase the size of the channel to control the amount of current. JFETs can operate only in depletion mode. There are two types of MOSFETS: depletion-type MOSFETs or D-MOSFETs, and enhancement-type MOSFETs, or E-MOSFETs. There are two types of channel: n-channel and p-channel. We will use the n-channel MOSFETs to describe the basic operation, as shown in Figure 7.29, and 7.30. The p-channel MOSFETs is the same, except the voltage polarities are opposite those of the n-channel.

Figure 7.29 N-Channel depletion-type MOSFET Here,  The channel already exists.  An input voltage to the gate will increase or decrease the channel size. 298 | P a g e

Figure 7.30 N-Channel enhancement-type MOSFET(NMOS)

Here,  The device has no channel.  An input voltage to the gate will form a channel.

Depletion MOSFET (D-MOSFET) [5] The first type of MOSFET is the depletion MOSFET (D-MOSFET), and Figure 7.31 illustrates its basic structure. The drain and source are diffused into the substrate material and then connected by a narrow channel adjacent to the insulated gate. Both n-channel and p-channel devices are shown in the figure. We will use the n-channel device to describe the basic operation. The p-channel operation is the same, except the voltage polarities are opposite those of the n-channel.

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Figure 7.31 Representation of the basic structure of D-MOSFETs. [5]

The D-MOSFET can be operated in either of two modes—the depletion mode or the enhancement mode — and is sometimes called a depletion/enhancement MOSFET. Since the gate is insulated from the channel, either a positive or a negative gate voltage can be applied. The n-channel MOSFET operates in the depletion mode when a negative gate-to-source voltage is applied and in the enhancement mode when a positive gate-to-source voltage is applied. These devices are generally operated in the depletion mode. Depletion Mode: Visualize the gate as one plate of a parallel-plate capacitor and the channel as the other plate. The silicon dioxide insulating layer is the dielectric. With a negative gate voltage, the negative charges on the gate repel conduction electrons from the channel, leaving positive ions in their place. Thereby, the n channel is depleted of some of its electrons, thus decreasing the channel conductivity. The greater the negative voltage on the gate, the greater the depletion of n-channel electrons. At a sufficiently negative gate-to-source voltage, VGS(off), the channel is totally depleted and the drain current is zero. This depletion mode is illustrated in Figure 7.32 (a). Like the n-channel JFET, the n-channel D-MOSFET conducts drain current for gate-to-source voltages between VGS(off ) and zero. In addition, the D-MOSFET conducts for values of VGS above zero.

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Enhancement Mode: With a positive gate voltage, more conduction electrons are attracted into the channel, thus increasing (enhancing) the channel conductivity, as illustrated in Figure 7.32 (b).

Figure 7.32 Operation of n-channel D-MOSFET. [5]

D-MOSFET Symbols: The schematic symbols for both the n-channel and the p channel depletion MOSFETs are shown in Figure 7.33. The substrate, indicated by the arrow, is normally (but not always) connected internally to the source.

Figure 7.33 D-MOSFET schematic symbols. [5] 301 | P a g e

D-MOSFET Transfer Characteristic: The D-MOSFET has the same transconductance curve and equation as the JFET.

Figure 7.34 Transconductance curve of D-MOSFET.

Example 11: For a certain D-MOSFET, IDSS = 10 mA and VGS(off) = – 8 V. (a) Calculate ID at VGS = – 3 V. (b) Calculate ID at VGS = +3 V. Solution: The device has a negative VGS(off); therefore, it is an n-channel D-MOSFET.

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Figure 7.35 For Example 11.

Example 12: For a certain D-MOSFET, IDSS = 18 mA and VGS(off) = +10 V. (a) Is this an n-channel or p-channel? (b) Calculate ID at VGS = +4 V. (c) Calculate ID at VGS = -4 V. Solution: (a) The device has a positive VGS(off). Therefore, it is a p-channel D-MOSFET.

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D-MOSFET Biasing Circuits [2] Recall that D-MOSFETs can be operated with either positive or negative values of VGS. A simple bias method is to set VGS = 0 V. A MOSFET with zero bias is shown is Figure 7.36.

Figure 7.36 A zero-biased D-MOSFET. [2] The drain-to-source voltage is expressed as: 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑆𝑆 𝑅𝐷

Example 13: Determine the drain-to-source in the circuit of figure 19. Assume VGS(off) = -8 V, IDSS = 12 mA, VDD = 18 V, RD = 620  and RG = 10 M . Solution:

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Enhancement MOSFET (E-MOSFET) [5] The E-MOSFET operates only in the enhancement mode and has no depletion mode. It differs in construction from the D-MOSFET in that it has no structural channel. Notice in Figure 7.37(a) that the substrate extends completely to the SiO2 layer. For an n-channel device, a positive gate voltage above a threshold value induces a channel by creating a thin layer of negative charges in the substrate region adjacent to the SiO2 layer, as shown in Figure 7.37(b). The conductivity of the channel is enhanced by increasing the gate-to-source voltage and thus pulling more electrons into the channel area. For any gate voltage below the threshold value, there is no channel.

Figure 7.37 The basic E-MOSFET construction and operation (n-channel). [5] The schematic symbols for the n-channel and p-channel E-MOSFETs are shown in Figure 7.38. The broken lines symbolize the absence of a physical channel. An inward-pointing substrate arrow is for n channel, and an outwardpointing arrow is for p channel.

Figure 7.38 E-MOSFET symbols. [5] 305 | P a g e

E-MOSFET Transfer Characteristic: The E-MOSFET uses only channel enhancement. Therefore, an n-channel device requires a positive gate-to-source voltage, and a p-channel device requires a negative gate-to-source voltage. Figure 7.39 shows the general transfer characteristic curves for both types of E-MOSFETs. As you can see, there is no drain current when VGS = 0. Therefore, the E-MOSFET does not have a significant IDSS parameter, as do the JFET and the D-MOSFET. Notice also that there is ideally no drain current until VGS reaches a certain nonzero value called the threshold voltage, VGS(th).

Figure 7.39 E-MOSFET general transfer characteristic curves. [5]

The value of ID at a given value of VGS, can be determined by

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Example 14: For a 2N7008 E-MOSFET with ID(on) = 500 mA at VGS(on) = 10 V and VGS(th) = 1 V. Determine the drain current for VGS = 5 V. Solution:

Next, using the value of k, calculate ID for VGS = 5V

Figure 7.40 For Example 14.

E-MOSFET Biasing Circuits [5] Recall that D-MOSFETs must have a VGS greater than the threshold value, VGS(th), so zero bias cannot be used. Figure 7.41 shows voltage-divider bias circuit of an E-MOSFET. In the voltage-divider, the purpose is to make the gate voltage more positive than the source by an amount exceeding V GS(th). Equations for the analysis of the voltage-divider bias become:

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Figure 7.41 Voltage-divider bias of n-channel E-MOSFET. [5]

Figure 7.42 shows drain-feedback bias circuit of an n-channel EMOSFET. In the drain-feedback bias circuit, the purpose is also to make the gate voltage more positive than the source by an amount exceeding V GS(th). In the drainfeedback bias circuit, there is a negligible gate current and, therefore, no voltage drop across RG. This makes VGS = VDS

Figure 7.42 Drain-feedback bias of n-channel E-MOSFET. [5] 308 | P a g e

Example 15: Determine VGS and VDS for the E-MOSFET circuit. Assume this MOSFET has ID(on) = 200 mA at VGS = 4 V and VGS(th) = 2 V.

Figure 7.43 For Example 15. [5]

Solution:

Therefore, Q-point is at ID = 63.8 mA and VGS = 3.13 V.

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Example 16: Determine the amount of drain current for the circuit shown in Figure 7.44. The MOSFET has a VGS(th) = 3 V.

Figure 7.44 For Example 16. [5] Solution:

Therefore

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