DC-coupled, single-to-differential design solutions using fully

DC-coupled, single-to-differential design solutions using fully differential amplifiers (Part 1 of 2) Michael Steffes, Sr. Applications Manager, Intersil Corp. Since the emergence of the wideband fully differential amplifier (FDA) topology with the introduction of the AD8138 in 1999, a popular application of this type of device has been to convert a single-ended input to a differential signal around some common-mode voltage. This is a typical requirement to drive all modern, high-speed ADC’s. At higher speeds, where a doubly terminated transmission line-type environment is desirable, a common application would be to present a defined, single-ended input impedance to match some source impedance. Then, the FDA converts that single-ended input into a differential signal with some gain centered on the Vcm of the ADC. Thus far, a closed-form solution for the resistor values in this application of the FDA has proven remarkably elusive, with iterative techniques the current norm. While effective, these huntand-peck solutions miss some of the more useful insights a closed-form solution can provide. Building on previous work, an exact solution for the required resistors will be presented here along with a design example using the 4-GHz ISL55210 FDA and the low-power, 10-bit, 500MSPS ISLA110P50 ADC.

DC-coupled, single-to-differential, wideband FDA applications circuit The topology for consideration is shown in Figure 1. This application is intended to provide a defined input impedance matched to a known source impedance (Rs) and give the resulting input signal at the Rt node a gain of Av to the differential outputs centered on a controlled common mode voltage set by the Vcm control input.

Figure 1. DC-coupled, single-to-differential circuit with input-impedance matching-analysis circuit

This is one of those deceptively simple-looking circuits that quickly sinks into an algebraic morass as layer after layer of issues are considered. A general analysis of this circuit with unconstrained resistor values leads to masses of equations that provide only modest benefit but a rigorous foundation for some very useful simplifications (Reference 1 and Reference 2). To move forward quickly with this discussion, those simplifications include using equal feedback resistor values and that the feedback voltage divider from each output back towards the input nodes (+ & - in Figure 1) be set equal. One goal of this circuit is to have an output signal that is purely differential around the Vcm DC bias voltage. FDA application circuits will benefit from a matched voltage divider back to the feedback points to eliminate any input signal to common mode output conversion. In the circuit of Figure 1, we would like the signal at Vi to only produce an output differential signal that is Av × Vi with no modulation of the Vcm voltage that is signal related particularly as the frequencies increase and the loop gains roll off. Matching the feedback divider ratios is required to achieve this. If the feedback resistors are set equal, then that constraint can be described by Equation 1.

Rg 2

Rg1

Rt || Rs

Eq. 1

The next key insight to move towards a resistor-value solution in Figure 1 is to recognize that the impedance looking in towards Rg1 is not simply Rg1 as it normally would be in an inverting op amp type application. While in some applications of the FDA this would be true (see Reference 3, for an example of an FDA application where the FDA summing junction voltages have no input signal component other than the differential loop gain error voltage), in this single-to-differential configuration, the input voltages at the FDA summing junctions are moving with the input signal. It is critical to recognize that two loops are operating in most FDA devices. The differential loop will force the differential input voltage across V+ and V- in Figure 1 to be ideally zero, but the common-mode loop is moving the common-mode input voltage with the input signal to hold the output Vcm constant. So, imagine Vi in Figure 1 moving up in voltage with a fixed output Vcm. This will cause the common-mode voltage at the FDA inputs to move up also along with the input signal. This has the effect of making the apparent input impedance looking into Rg1 to be higher than simply Rg1 as the amplifier V+ node is essentially a driven source that has a Vs dependence in the direction of resisting current flow into the Rg1 resistor – increasing the apparent input impedance over just Rg1.

It is this “active input termination” aspect of Figure 1 that has led to the iterative solution methodologies used prior to the solutions presented here.

Closed-form solutions for the resistors in the single-to-differential FDA application Drawing on some recent summary work by Jim Karki, where he recognizes and delivers this active input impedance equation and gain in Equations 8 and 9 in Reference 4, we can use his performance equations to start a solution for Rt that will simultaneously achieve the desired input match and deliver the desired gain while holding the feedback divider ratio’s matched. Both References 2 and 4 define feedback divider expressions to simplify the equations, repeated as Equation 2 and Equation 3 here.

Rg1 Rg1

Eq. 2

Rf Rg 2

Rg 2

Eq. 3

Rf

The full voltage-divider equation back to the V+ input of Figure 1 will also be constrained to equal β-. These two β's will therefore be unequal for this DC-coupled single-to-differential application circuit. The resulting circuits will have a “Noise Gain” that can be easily recognized to be 1/β-. This can be used with voltage feedback amplifer (VFA)-based FDAs to estimate their resulting closed-loop signal bandwidth. If the Gain Bandwidth Product (GBP) is reported, then a good estimate of closed loop signal bandwidth will be GBP × βUsing these β’s, Reference 4 reports an apparent input impedance looking into Rg1 as a ZA (active impedance) term given by Equation 4. (Equation 8 in Reference 4)

ZA

( R g1

Rf )

(

) 1

Eq. 4.

This active termination appears in parallel with Rt to set the total apparent input impedance at Vi in Figure 1. Assuming this condition is achieved, then the differential-gain expression is given as Equation 5 (Equation 9, Reference 4).

Av

2

Rf R g1

( Rs || Rt ) Rt

Eq. 5

Rt Rs

Everything is here to solve for Rt, but it is definitely a non-trivial exercise to pursue manually. These active input-impedance solutions seem to generally result in a quadratic solution for the target element. [See Reference 5 for a similar example in the solution for a complementary DAC output to single ended using the single op amp configuration – legacy designs failed to recognize there that the inverting node on the op amp is in fact dependent on the non-inverting voltage and hence dependent on the signal – so the inverting path of that circuit also has an active termination piece and the solution there is also quadratic]. Here, the quadratic solution for Rt is shown as Equation 6 (Reference 6) where the Rg elements have been eliminated and we are left with only the target gain, source resistor and feedback resistor value to get a solution for Rt

2 t

R

Rs 2 Av ) 2 Av ) Rs Av (4 Av )

2 Rs (2 R f

Rt

2 R f (2

2 R f Rs2 Av 2 R f (2

Av ) Rs Av (4

Av )

0

Eq. 6

Once we have the Rt required to simultaneously satisfy the input impedance at Vi ( Rt||ZA = Rs ) and hit the desired gain, Av, the two Rg resistors are set using Equation 7 and Equation 8.

`R

Rf

2

Av

g1

1 2 Rg 2 1

Rs Rs Rt

Eq. 7

Rf Av Rs Rt

Eq. 8

The design solutions delivered by Equations 6 through 8 were initially verified through numerous example designs in ADS using the Intersil ISL55210 wideband FDA full transistor model (Reference 7). One outcome of having the closed form solution for Rt of Equation 6 is that buried in the solution for Rt is an expression that allows us to solve for the maximum achievable Av given Rf

and Rs. Looking at Equation 6, where the denominator part of the coefficients goes to zero, an infinite solution for Rt will result. Solving for that, gives an expression for Avmax if an Rf and Rs have been chosen.

Av max

(

Rf Rs

4 2 ) (1

1 (

Rf Rs

Rf Rs 2)

)

Eq. 9.

2

It is apparent from Equation 9 that once you have picked an Rf and are given an Rs, there is a topological constraint on the maximum achievable gain in the circuit of Figure 1. Most designs do start by picking an Rf and then flowing from there – considerations on picking Rf include – 1. If the FDA is a Current Feedback Amplifier (CFA) type, Rf sets the bandwidth control. 2. Rf appears as part of the output load in this topology, very low values can start to impair the output distortion 3. Rf also enters into the total output noise equation. It acts as the gain for the input current noise terms and adds its own thermal noise. So very high values can start to impact output noise excessively. This is particularly true for Current Feedback based FDAs which will also have higher summing junction current noise terms vs. VFA based FDAs. 4. Very high values of Rf for a Voltage Feedback type FDA can also start to introduce an additional feedback pole due to the parasitic input C's on the FDA summing junctions. This can sometimes hurt the phase margin ,introducing possible peaking or instability depending on the device and gain setting. Normally, for Voltage Feedback Amplifier (VFA)-based FDA devices, where the Rf value has considerably more flexibility than Current Feedback Amplifier (CFA) based FDA devices, an Rf value in the 200Ω to 1500Ω is most common. It is interesting to plot Equation 9 for several target Rs values over Rf to set an upper bound on the achievable gain in the circuit of Figure 1. Figure 2 shows this in linear terms while Figure 3 shows log gain and a log scale on Rf.

Max. Achievable Gain (V/V)

Max. Voltage gain vs Rf and Rs 90 80 70 60 50 40 30 20 10 0

Rs=50 Rs=75 Rs=90

200

700

1200

1700

Feedback Resistors value (Ω)

Figure 2. Maximum achievable gain vs. Rf parametric on Rs.

Max. Voltage Gain vs Rf and Rs Max. Achievable Gain (dB)

40 35 30 25

Rs=50

20

Rs=75

15

Rs=90

10 100

1000 Feedback Resistors Value (Ω)

Figure 3. Maximum achievable dB gain vs. Rf parametric on Rs.

An alternative way to use the denominator expressions in Equation 6 would be to use a targeted Rs and Av and solve for the Rf value that will force the Rt to infinity – giving only an Rg1 based active input termination. Doing this gives Equation 10 for an Rfmax to force Rt to infinity.

R f max

Av ( Av 2 ( Av

4 ) Rs 2)

Eq.10

Running an example design using Equation 10, target a gain of 10V/V with Rs = 50Ω. Equation 10 gives a required Rfmax = 292Ω and then an Rg1 = 8.39Ω and Rg2 = 58.3Ω. Snapping these values to closest 1% gives circuit of Figure 4 where no Rt element is used, but the input impedance will appear as 50Ω. Putting the element values of Figure 4 back into the ZA (Equation 4) gives an input impedance of 50Ω.

Figure 4. Gain of 10V/V with no Rt termination and 50Ω input match. One possible outcome of a purely active input-termination circuit is a lower equivalent inputreferred noise. Figure 5 shows an ADS simulated output noise for the example of Figure 4 which will be including all the internal noise elements of the design.

Figure 5. Differential output spot noise simulation for the circuit of Figure 4.

This total output noise includes the source-resistor noise of 0.89nV/√Hz divided down by the equivalent 50Ω input match to 0.48nv/√Hz, then gained up by 10 to be a 4.8nV/√Hz output spot noise contribution. The red curve below is the total output noise with the blue curve the total input referred noise. The 9.8nV/√Hz at the output means the non-source noise related terms are at approximately 8.54nV/√Hz. Input referred by the gain of 10 gives approximately 0.85nV/√Hz – very close to the specified differential voltage noise for the ISL55210 by itself. So indeed, this active termination seems to be delivering an input referred noise of just the amplifier voltage noise with very little added resistor noise terms. The NF expression from this input referred spot noise voltage is given as Equation 11. The ei here is the spot noise at Vi exclusive of any noise delivered by the source resistor.

NF

10

log ( 1

ei2 ) Rs kT

Eq. 11

Putting in numbers gives a Noise Figure of 6.6dB for the circuit of Figure 4. This is using ei = 0.85nV/√Hz Rs = 50Ω kT = 4 × 10-21 Joule

High-gain amplifier designs with other considerations It is somewhat surprising how high the gains can be and still achieve an input match. This comes from the Rg1 solving for values 0V. This will cause a DC current to be delivered back towards the source that must be considered. So while it would normally be assumed that Vs must deliver current to the Vi point, it is actually sinking current in most cases. This current is essentially providing the common mode level shift to the outputs of the FDA, which are most often at a positive voltage above ground to get the differential voltage swing matching up with the input range of an ADC.

References 1. “Fully Differential Amplifiers Application Report”, Jim Karki, Texas Instruments application note SLOA054. http://focus.ti.com.cn/cn/lit/an/sloa054d/sloa054d.pdf

2. “High Speed Differential ADC Driver Design Considerations”, John Ardizzoni & Johnathan Pearson, Analog Devices application note AN-1026. http://www.analog.com/static/imported-files/application_notes/AN-1026.pdf 3. “Deliver the lowest distortion and noise in a low-power, wideband, ADC interface (Part 1 of 4)”, Michael Steffes, Planet Analog, 4/25/2011. http://www.eetimes.com/design/analog-design/4215415/Deliver-the-lowest-distortionand-noise-in-a-low-power--wideband--ADC-interface--Part-1-of-44. “Input impedance matching with fully differential amplifiers”, Jim Karki, TI Analog Applications Journal 4Q 2008, pp24-28. http://focus.ti.com/lit/an/slyt310/slyt310.pdf 5. “Wideband Complementary Current Output DAC to Single-Ended Interface: Improved Matching for the Gain and Compliance Voltage Swing”, Michael Steffes, Texas Instruments application note, SBAA135, June 2005. http://focus.ti.com/lit/an/sbaa135/sbaa135.pdf 6. Contact the author for the detailed derivation of this equation. 7 “Wideband, Low Power, Ultra High Dynamic Range Differential Amplifier”, Intersil ISL55210 http://www.intersil.com/data/fn/fn7811.pdf 8. “10-Bit, 500MSPS, ADC Converter” ISLA110P50, http://www.intersil.com/data/fn/fn7606.pdf 9. Intersil’s free power and spice simulator download, iSim PE http://web.transim.com/iSim/download/iSimPE.aspx 10. Contact the author for the design flows to these filters and/or example filter files in iSim PE

About the author Michael Steffes is Senior Applications Manager, Intersil Corp. with more than 25 years of experience in high-speed amplifier design, applications, and marketing. Previously, he was the Market Development Manager for High-Speed Signal Conditioning, and a Distinguished Member of the Technical Staff, at Texas Instruments Inc. He currently provides product definition and customer design-in support. Michael earned a BSEE from the University of Kansas and an MBA from Colorado State University. He shares several basic patents in high-speed op amp designs and has written more than 85 product data sheets, scores of contributed articles, applications notes and conference papers.