MOSFET Selection to Minimize Losses in Low-Output

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

MOSFET Selection to Minimize Losses in Low-Output-Voltage DC-DC Converters. Jon Gladish, Fairchild Semiconductor

Abstract — This paper focuses on the role of the power MOSFET in achieving high-efficiency converter design. It provides a brief overview of current low-voltage MOSFET trench technologies, along with a discussion about onresistance versus gate charge trade-offs for MOSFETs optimized for use as control or synchronous switches. It covers the importance of the integrated Schottky diode (SyncFET™ MOSFET) in synchronous rectification and the necessity for packaging technologies with low parasitic inductance and resistance. The MOSFET-to-circuit interaction is discussed in detail, with TCAD mixed-mode simulations. All relevant MOSFET switching events are analyzed: common-source inductance versus drain current rise and fall, body diode conduction and reverse recovery, external Schottky diode layout challenges versus SyncFET MOSFET advantages, and elimination of shoot-through currents from gate bounce. The simulated MOSFET power losses are compared for various circuit inductance cases and used for background in discussing measured converter efficiency data. A review of popular MOSFET loss equations is also discussed.

I. INTRODUCTION The low-output-voltage DC-DC regulator is the basic building block for essentially all CPUs, memory, chipsets, and auxiliary supplies. Many of the CPU or GPU ICs are demanding DC-DC converters deliver a very high output current at a very low output voltage with ever-increasing load current slew rate requirements. There is also a simultaneous drive to minimize both printed circuit board (PCB) temperatures and converter sizes as many PCBs are already fully populated with ICs that can do without the heat coupling arising from nearby inefficient power converters. Finally, the converter must not induce excessive conducted or radiated EMI into the surroundings, which requires special attention to layout paths and proper selection of components. For such switching converters, the power MOSFET silicon and packaging technology play important roles in realizing these design goals. The process of selecting power MOSFETs for a DC-DC converter design often begins with a

designer narrowing down a selection of MOSFETs based upon a few key parameters. Parameters (or features) such as the minimum guaranteed drainsource breakdown voltage (BVDSS), package type (i.e. SO-8, TO-252, etc.), on-resistance (RDS(ON)), and Figure-of-Merit (FOM), or [RDS(ON)] x Total Gate Charge [QG(TOT)], typically give significant insight into the expected MOSFET performance. These parameters, combined with various other datasheet parameters, are typically used within a spreadsheet loss analysis to predict efficiencies based on conduction and switching losses. MOSFET loss equations formulated around piecewise linear approximations of switching waveforms are found frequently in MOSFET supplier application notes. A review of application notes[1][2][3] from some power MOSFET and power management suppliers reveals that there is industry agreement for generalized MOSFET loss equations. The set of loss equations generally gives the converter designer an idea of the MOSFET conduction and switching losses, but may fall short of actual measured data. Loss calculators often underestimate MOSFET switching losses since they omit the influence of parasitic circuit inductance. This paper takes an in-depth look into the losses associated with power MOSFET switching transitions and, through simulations, compares ideal and non-ideal cases. While the discussion is centered around the synchronous buck converter, many of the parametric selection criteria also applies to isolated DC-DC converters where a primary-side MOSFET closely resembles the highside control MOSFET and the output or secondaryside rectifiers resemble the low side synchronous MOSFET. II. DISCRETE POWER MOSFETS Discrete power MOSFETs are available within a vast combination of RDS(ON), BVDSS and packaging options. The multiple combinations are typically 1

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

Packaged RDSON (mΩ )

6 5

VGS = 10V

4 3 2 1 0 1998

2003 Year Introduced

2008

Fig. 1. RDS(ON) vs. Time [30V BVDSS MOSFET in an SO-8 footprint]. 100 FOM QGD x RDS(ON)

1. Very low on-resistance is essential for minimizing synchronous rectifier and controlling MOSFET conduction losses. Low RDS(ON) in a discrete MOSFET implies that the package and the silicon resistive contributions are very low. Modern low-voltage discrete power MOSFETs give special attention to minimizing package resistance, since a packaged MOSFET approaching the one milliohm level may have 30% or more of the total resistance as package bond wire and lead resistance. Figure 1 provides curve-fitted industry data for a typical 30V packaged MOSFET RDS(ON) versus time (SO-8 footprint). 2. Low FOM is essential for optimizing control MOSFET switching and conduction losses and is typically needed for the prevention of synchronous rectifier [CGD x dVDS/dt] induced turn-on. While there are many metrics used to grade switching MOSFETs, the RDS(ON) x QG(TOT) (or QGD) FOM are the most common and typically correlate with high performance. While it can be argued that there are subtle differences in each FOM, a lower RDS(ON) x QGD FOM typically signifies a higher switching grade MOSFET and often correlates to lower RDS(ON) x QG(TOT). Figures 2 and 3 plot some industry averages for MOSFET figure of merit versus time. 3. Low internal series gate resistance (RG or gate ESR) is important. A discrete power MOSFET is often depicted (or modeled) as a lumped

circuit consisting of parasitic capacitance and resistance of the active cell scaled for area, where the MOSFET internal gate resistance and internal capacitance determine the input impedance and switching speeds.

VGS 4.5V 10V

50

0 1998

2003

2008

Year Introduced

Fig. 2. QGD x RDS(ON) FOM vs. Time.

300 FOM (QTOTAL x RDSON )

made available by a supplier to suit the needs of a large array of applications, ranging from lower performance, cost-sensitive designs to harsh environment, high-reliability designs to highperformance designs where optimized packaging and silicon need to be fully utilized. Typically, these higher performance converter designs push MOSFET silicon and packaging technologies to strive for smaller, more efficient products. It is essential that MOSFETs designed for high-efficiency, high-switching-frequency applications (> 300 kHz) have a few key attributes for meeting the ever-increasing demand for high power densities with high converter efficiency. The key attributes are:

10V RDSON x QTOT(10)

200

4.5V RDSON x QTOT(4.5)

100

0 1998

2003 Year Introduced

2008

Fig. 3. QG(TOT) x RDS(ON) FOM vs. Time.

4. Low parasitic package inductance, which is important for optimizing MOSFET switching speed and is required for minimizing the voltage stresses associated with L x di/dt during switching transitions. 5. Low thermal resistance (junction-to-case, ΘJC and junction-to-ambient, ΘJA) for removal of 2

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

self-generated heat from the MOSFET silicon and package increases reliability and provides for minimized power losses with higher system efficiencies. 6. Robust Forward Biased Safe Operating Area (FBSOA) and Unclamped Inductive Switching (UIS) are typically highly correlated and provide insurance for surviving high-energy switching spikes within the converter. A. Packaging Technologies As previously mentioned, power MOSFET silicon is supplied within various packaging technologies to accommodate the vast number of applications where these products may be used. For example, very small footprint Chip-Scale (CSP) or Ball Grid Array (BGA) package, shown in Figure 4, provides a very low height profile, along with exceptional die-to-footprint ratio, optimizing space-constrained systems. They also tend to offer the lowest parasitic resistance and inductance due to their direct connection to the PCB. They can be found in ultraportable electronics operating as load switches or used in low-current switching converters. However, larger high-current BGA packages have also been demonstrated as excellent candidates for realizing high efficiencies in very high-frequency switching converters[4][5].

copper clip bonded. Each of these techniques, especially source and gate bonding, influences the packaging parasitic inductance and resistance. While packaging resistance is part of the aggregate RDS(ON) reported on datasheets, packaging inductance is rarely stated. This value can be approximated through lab measurement or can sometimes be found in a MOSFET supplier’s SPICE or SABER® model[6]. PQFN and MLP also offer very low junction-to-case thermal resistance due to the exposed copper header.

Drain Source Bond Wires Fig. 5. - MLP 5mm x 6mm.

The larger TO-220 or TO-252 (D-PAK) package, shown in Figure 6, is typically found in automotive, industrial, or computer applications, such as desktop mother- and daughter-board voltage regulators where PCB real estate is larger. Source Bond Wires

Source Drain BGA 1.5mm x 1.5mm

CSP 1.0mm x 1.5mm

Fig. 4. - BGA and CSP packages.

The somewhat larger, but still very efficient, fully encapsulated Power Quad (and Dual) Flat Package (PQFN or DFN), Micro Lead-frame Package (MLP) shown in Figure 5, or SO-8, are some of the most popular packages found in DC-DC converter designs (for discussion purposes in this paper, PQFN and MLP are treated as similar packages). All three packages provide good die-to-footprint ratios and can provide low parasitic resistance and inductance. Internally, the die attach (typically the MOSFET drain) can be soldered or epoxy bonded, while the source and gate connections can be copper/gold/aluminum wire or ribbon bonded, or

Gate Bond Wire

Fig. 6. - TO-252 (D-PAK).

These packages offer excellent junction-to-case thermal resistance with large copper headers that provide for heat-sinking. They also typically have the highest maximum rated operational temperature range, a feature highly desirable in automotive and industrial applications. However, the long lead and bond wire lengths tend to create much higher parasitic inductance compared to PQFN or SO-8, shown in Figure 7. Packaging parasitics are discussed in detail in reference [7]. Another drawback is that the die-to-footprint ratio is less desirable than PQFN or SO-8, which unnecessarily occupies valuable PCB space.

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FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

Inductance ( nH )

4

SOURCE METAL

LGate (D-PAK)

P+ contact

N+ Source

3

dielectric LSource (D-PAK)

2

LGate (PQFN)

1

Gate

CDS

LSource (PQFN)

Drain

P type Body

CGS CGD

0 1

10 Frequency ( MHz )

Channel N- Epi

100

Fig. 7. Package parasitic inductance versus frequency.

B. Silicon Technologies The active cell structure of a low-voltage discrete power MOSFET is often described by the two dimensional cross section of the cell or cells, shown in Figure 8 (not drawn to scale - depicts the typical repetitive nature of the cell). While MOSFET technologies and cell structures have evolved dramatically through the years, the MOSFET cell structure can be segmented into three basic categories: planar, trench or lateral. Of the three structures, trench-gated MOSFETs are most common for high-performance discrete power MOSFETs with BVDSS < 200 V. They are chosen primarily for their exceptionally low specific onresistance (product of resistance times area of silicon – measured in milliohm-mm2 (or cm2)), and are a technology capable of excellent RDS(ON) x QG(TOT) (QGD) FOM across the BVDSS spectrum. They also tend to provide for a very robust FBSOA and UIS for surviving harsh switching events. A compelling advantage of the trench structure is in the ability to reduce on-resistance by providing the shortest possible current path (vertical) from drain to source through the lowest possible resistance. As shown in Figure 8, the major contributors to silicon resistance typically arise from the channel (RCHANNEL), epitaxial (drift region) REPI, and substrate regions RSUBSTRATE.

N+ Substrate

Drain Metal Fig. 8. Trench Power MOSFET active cell cross section.

The substrate and epi-resistances are often controlled by utilizing the thinnest, highest doped silicon possible. While the ability to achieve tight trench-to-trench cell pitch allows for an extremely high channel width-to-length ratio (W/L), this results in a very low channel resistance. Drain Gate

CGD CDS

RG Gate Thick oxide for low CGD

CGS Source

Fig. 9. Trench MOSFET cell with Thick Bottom Oxide (TBO).

The percentage of resistance associated with each region varies dramatically, depending on design and BVDSS. While RDS(ON) is vital for low conduction losses, considerations must be made for enhanced FOM, where trade-offs in trench depths and widths exist to optimize the structure. Variations to the standard trench cell of Figure 8 are often designed with the intention of preserving low resistance, while enhancing the FOM. Structures such as the shielded gate or thick bottom 4

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

oxide trench, shown in Figure 9, are two examples that limit the gate-to-drain overlap capacitance, thus lowering QGD and providing faster switching and increased dv/dt immunity. C. Integrated Schottky Diode (SyncFET MOSFET) The monolithically integrated Schottky diode can be one of the most important features added to the low-side MOSFET die, especially as the input DC input voltage increases. A well-designed Schottky diode can simultaneously decrease the dead time diode conduction losses and dramatically reduce switching losses attributed to QRR. This provides added output capacitance to reduce the recovery dVDS/dt, assisting in the prevention C x dVDS/dt turn-on. Schottky contact

Drain Source

Gate

Schottky diode cell

Source

Fig. 10. Trench Metal Barrier Schottky (TMBS) cell (SyncFET)

A typical Trench Metal Barrier Schottky (TMBS) active cell is shown in Figure 10. This type of Schottky diode structure integrates well into the trench MOSFET, as it utilizes a trench structure as an integral part of the overall Schottky diode structure. The Schottky diode cell can be distributed through the MOSFET active area or placed separately in a dedicated area on the die, providing an extremely small physical separation from the MOSFET body diode. Both methods provide reduced body diode injection and QRR[8]. The Schottky diode contact is typically formed on the topside of the structure where the N-type silicon and metal form the Schottky diode barrier, while the trench poly-silicon is often tied directly to source metal that aids in providing a high breakdown in the cell, along with enhanced robustness.

III. SYNCHRONOUS BUCK CONVERTER The non-isolated synchronous buck converter, shown in Figure 11, is widely used throughout electronic systems to step down an intermediate DC bus voltage to a logic level voltage powering a CPU, GPU, memory, or other integrated circuits. LF

Q1

VIN

Controller and Driver

Q2

CF

VO RLOAD

Fig. 11. Synchronous buck schematic.

The synchronous buck converter is used in this paper as an evaluation platform for discussing power MOSFET losses due to the popularity and relative ease and convenience of evaluating a control MOSFET (hard–switched) and synchronous MOSFET in one circuit. The MOSFET loss equations presented correspond to the synchronous buck converter operating waveforms in the steady-state, continuous conduction mode (CCM). The equations are presented with the corresponding power MOSFET switching waveforms, which aid in loss explanations. For this discussion, it is assumed the reader has a basic knowledge of the buck converter operation and is encouraged to read references [9] and [10] for a more in-depth description of the theory behind the synchronous buck operation. The MOSFET loss discussions are intended to review the ideal switching waveforms (no circuit inductance) and transition into the more realistic waveforms that include the effects from parasitic package and circuit inductance. Then, with the aid of simulation and measured waveforms, the discussion explores each switching transition and points out potential issues that may arise, causing MOSFET switching to deviate from predicted results. Finally, various converter efficiency curves are shown to correlate to the switching waveforms.

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FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

IV. MOSFET LOSSES Generally, MOSFET losses can be categorized as either switching or conduction losses, where the total loss across one switching cycle equals the sum of the switching and conduction losses. A survey of typical loss equations from references [1], [2], and [3] are summarized in the following sections. A. High Side MOSFET (Q1) Loss From reference [1], the high-side MOSFET of the synchronous buck operates with an on-time equal to duty cycle, multiplied by switching period [D x TS]. The turn-off and turn-on switching currents are equal to the inductor ripple current, plus or minus the DC load current, respectively. Steady-state losses incurred by the high MOSFET are as follows: PLOSS (Q 1) = PCOND + PSW (ON ) + PSW (OFF ) + PGATE

(1)

PGATE (Q 1) = QG (TOT )VG fs

(2)

where: QG(TOT) = total gate charge of Q1; VG = Gate Drive DC voltage; fS = switching frequency, TS = 1/fS. PCOND (Q 1) = IQ2 1( RMS ) R DS (ON )( Q 1)

VIN IDS (OFF )tOFF 2

]fs

Q1 Turn-Off Loss

IDS(Q1)

VDS(Q1)

VGS(Q1)

VPlateau VTH t0

t1 QGD QGS2 Q2 VF Loss

ISD(Q2) VDS(Q2)

2

+

QOSSVIN + QRRVIN ]fs 2

where: IDS(ON) = inductor current at MOSFET turn-on; tON = (QGS2+QGD)/iG(ON); iG(ON) = (VG-VPLATEAU)/( RG_HS + RDRV_HSON); QOSS = output charge of Q1[3]; QRR = diode recovery charge of Q2.

VDSON(Q2) t3

t4

t5

t6

Fig. 12. MOSFET Q1 turn-off and Q2 turn-on loss waveforms.

(3)

(4)

1. Turn-off delay time (t1 – t0). During this phase, only the MOSFET RDS(ON) is affected as it rises in response to the lowering VGS. 2. Drain voltage rise time (t2 – t1), also known as the gate plateau or “Miller” region. During this switching event, VGS of Q1 is at a level where the MOSFET can no longer conduct the drain current at low VDS levels. Use Equation 6 for a linearly approximated value for VPLATEAU: VPLATEAU (OFF )Q1 =

VIN IDS(ON )tON

VTH

t2

where: VIN = Converter DC input voltage; IDS(OFF) = inductor current at MOSFET Q1 turn-off; tOFF = (QGS2+QGD)/iG(OFF); iG(OFF) = VPLATEAU/( RG_HS + RDRV_HSOFF). PSW (ON )Q1 = [

VGS(Q2)

Q2 COSS displacement current

Diode VF

where: RDS(ON)(Q1) = MOSFET on resistance; IQ1(RMS) = RMS drain current. PSW (OFF )Q1 = [

The switching characteristics of a control (hardswitching) MOSFET are a function of the MOSFET input impedance (capacitance CISS and resistance, RG) combined with the output impedance of the gate drive. The MOSFET turn-off process can be segmented in time into three phases shown in Figure 12.

(5)

I DS (OFF ) gm

+ VTH

(6)

where gm = MOSFET transconductance.

In response, VDS rises while VGS essentially stalls as the gate current charges the gate to drain capacitance, CGD. Instantaneous power losses can be large during this transition; there is simultaneous high drain current with rising drain voltage.

6

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009 PSW (OFF _ QGD )Q1 = [

VIN I DS (OFF ) (t 2 − t 1 ) 2

]fs

(7)

where: (t2 - t1) = QGD/ iG(OFF); QGD = gate to drain charge.

3. Current fall time (t3 – t2), gate discharge from VPLATEAU to VTH. During this transition, the channel of MOSFET Q1 is shut off while the inductor current is transferred to MOSFET Q2 body diode. The drain voltage of Q1 is clamped to the DC input bus by the body diode of MOSFET Q2 as the drain current begins to fall as VGS discharges. PSW (OFF _ QGS2)Q1 = [

VIN I DS(OFF ) (t 3 − t 2 ) 2

]fs

the diode tA phase (time t12 to t13) is large compared to the tB phase (time t13 to t14). During diode recovery, instantaneous power losses across the high-side MOSFET are large, since both the DC input voltage and diode recovery current, plus output inductor load current, remain across the high-side MOSFET until the low-side MOSFET can begin to block voltage (end of the tA phase). PSW (ON _ QGS 2 )Q1 = [

VDSIDS(ON ) (t12 − t11) 2

(9)

+ QRRVIN ]fs

where: (t12 - t11) = QGS2/ iG(ON); QGS2 = gate charge from VTH to VPLATEAU.

(8) Q1 Turn-On Loss

where: (t3 - t2) = QGS2/ iG(OFF); QGS2 = gate charge from VPLATEAU to VTH.

IDS(Q1) VDS(Q1)

The ideal high-side MOSFET turn-on process can also be segmented in time into three phases, shown in Figure 13. 1. Turn-off delay time (t11 – t10). During this phase the MOSFET is off with VGS rising toward VTH. 2. Current rise time (t12 – t11). The gate charges from VTH to VPLATEAU. During this switching event, the drain voltage of Q1 is clamped to the DC input bus since the body diode of Q2 is forward biased and conducting the inductor current. The drain current of Q1 begins to rise as VGS surpasses VTH. The inductor current is being transferred from Q2 to Q1. The current rise time ends once Q1 current equals the inductor current plus the peak reverse recovery current of Q2, IRR. For simplicity in loss calculations, the diode reverse recovery current is temporarily ignored to calculate the turn-on losses with an ideal diode. QRR losses are treated in a separate calculation. Figure 13 also shows the impact of diode reverse recovery on switching waveforms. The diode recovery time (tRR) and reverse recovery charge (QRR) specified on datasheets are generally used by loss calculators as a straightforward (QRR x fSW x VIN) switching losses. Referring to Figure 13, the assumption is that

VGS(Q1)

VPlateau VTH QGS2 QGD ISD(Q2) VGS(Q2) VTH

VDS(Q2) t7

t8

t9 t10

t11

t12

t13 t14

tA phase tB phase Fig. 13. MOSFET Q1 turn-on and Q2 turn-off loss waveforms.

3. The drain voltage fall time (t13 – t12) is the turnon gate plateau, or “Miller” region, where there is simultaneous high drain current with falling drain voltage. During this switching event, VGS of Q1 is at a level where the MOSFET conducts the entire inductor load current, plus the diode reverse recovery current. MOSFET (Q1) VDS begins to fall as the body diode enters the reverse blocking mode. Similar to the turn-off Miller region, VGS essentially stalls out as the gate current is used to discharge the gate to drain capacitance, CGD. 7

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

The drain voltage fall time also creates an internal MOSFET channel current due to the discharging output capacitance COSS. This current does not show in lab measurements, however, it is a switching loss and is typically treated with a separate loss contribution. An output charge, QOSS, which takes into account the non-linear effects of COSS as a function of VDS, is often used to calculate losses: PSW (ON _ QGD )Q1 = [

(IDS(ON ) (t13 − t12 ) + QOSS (Q1+Q 2) ) 2

]VIN fs

(10)

B. Low-Side MOSFET (Q2) Loss Typically, the low-side MOSFET is conductionloss dominated with additional diode conduction losses for dead times. Turn-on losses for Q2 is typically considered lossless since the transition is considered highly capacitive, as shown in Figure 12. The turn-off (diode recovery) event, shown in Figure 13, is approximated as near lossless because the QRR and QOSS are assumed to be dissipated in the high-side MOSFET turn-on. A more conservative technique is to add QOSS and QRR losses to Q2. Another actual switching event for Q2 discussed in reference [1] is switching between the MOSFET channel to body diode and vice versa. Losses are omitted here as the equations assume fast gate edges, however, for high-frequency operation, this switching event must be considered. Q2 losses are as follows:

P SWITCHING (OFF ) = [Q RR V IN +

Q OSS

( Q 2 )V IN

2

Note that both QRR and QOSS(Q2) are accounted for as losses in Q1 turn-on from Equation 10, however, a portion of these losses appears in Q2, with Equation 14 as guidance for distributing the losses. V. PARASITIC INDUCTANCE EFFECTS The loss equations presented above are generally used to estimate expected MOSFET performance, but often fall short of predicting actual performance. While there are numerous reasons this may occur, more often than not, the culprit is the parasitic circuit inductance, as shown in Figure 14. For lowvoltage MOSFETs, the influence of parasitic inductance has been studied rather intensely in recent years[11-13] and it has become general knowledge that inductance can strongly influence MOSFET switching characteristics, usually causing increased switching losses and deviations from the expected performance. Ld_HS Lg_HS

VIN

Rdrv_HS

Rg_HS

Control MOSFET

Ls_HS L_f

Ld_HS

PLOSS (Q 2) = PCOND(Q 2) + PSWITCHING (OFF ) + PGATE

(11)

PGATE ( Q 2 ) = Q G (TOT )( Q 2 )V G Fs QG(TOT)(Q2) = Total gate charge for MOSFET Q2.

(12)

PCOND (Q 2) = PMOS _ COND + PDIODE _ COND

(13)

_ COND

PDIODE

(Q 2 ) = I Q 2 ( RMS ) 2 R DS (ON )( Q 2 )

_ COND

(Q 2 ) = [I Q 2 (ON )V F t DEAD (ON ) +

R_snubber

Lg_LS Rg_LS Rdrv_LS

PMOS

(14)

]fs

R_load C_f

Synchronous MOSFET

C_snubber Ls_HS

(13a) (13b)

I Q 2 (OFF )V F t DEAD (OFF ) ]

where: PMOS_COND (Q2) = MOSFET Q2 channel conduction; PDIODE_COND (Q2) = Q2 body diode conduction; VF = Q2 body diode forward conduction voltage; TDEAD(ON) = dead time from Q1 (HS) off to Q2 (LS) on; IQ2(ON) = inductor current at Q2 (LS) turn on ( = IDS(OFF) Q1); TDEAD(OFF) = dead time from Q2 (LS) off to Q1 (HS) on; IQ2(OFF) = inductor current Q2 (LS) turn off (= IDS(ON) Q1).

Fig. 14. Synchronous buck with parasitic inductance.

Parasitic inductance arising from both component packaging and circuit layout is a reality of any circuit. The above packaging section shows that a package, such as the D-PAK, can have up to 2.5nH of inductance from bond wire and leads, which is added directly to the high-current / high-frequency AC loop inductance being minimized (the highcurrent AC loop is defined in Figure 20). Worse yet, when this inductance is common to both the gate and power loop (common source inductance 8

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

described in the following section), it tends to dictate the high-side MOSFET switching characteristics, causing slower switching and higher power losses. Zero Circuit Inductance Turn on loss VDS

Turn off loss

IDS

VGS

tON1

tOFF1

tON2

tOFF2

Including Circuit Inductance Turn on loss

Turn off loss IDS

VGS

tON1

tON2

tOFF1

tOFF2

Fig. 15. High-side switching waveform comparison - zero parasitic inductance (top) versus “typical” parasitic circuit inductance (lower).

Generic high-side MOSFET switching waveforms are shown in Figure 15. The waveforms for the parasitic inductance case are shown in side-by-side comparison to the zero parasitic inductance (ideal) case to clearly show the difference that arises in the switching edges and times. Often, loop inductance adds significant voltage stresses to the MOSFET, arising from the fast circuit di/dt during turn on and turn off. Note that unless stated otherwise, all MOSFET gate-to-source VGS and drain-to-source VDS waveforms are defined at the silicon level, excluding parasitic resistance and inductance. While closed-form equations have been derived for MOSFET switching losses, including the effects

of circuit inductance[11][12][13], this paper relies on advanced simulations to quantify circuit-toMOSFET interactions. A. TCAD Mixed-Mode Simulations Technology Computer Aided Design (TCAD) mixed-mode simulations are arguably the most accurate method of modeling power MOSFET losses[14]. TCAD software is typically used by semiconductor devices and process engineers for device development and modeling and is extremely useful in modeling MOSFET silicon and package interactions. The concept is to utilize a highly accurate and calibrated physical MOSFET model in combination with behavioral circuit elements to accurately model MOSFET switching behavior. A benefit of this simulation over SPICE is the very accurate modeling for diode QRR, dynamic avalanche, and other minority carrier effects. For this paper, a TCAD mixed-mode simulation was set up to predict losses for a single-phase, wideinput voltage converter (i.e. 7-22VIN for a typical Notebook computer). While all reported simulation losses are shown at 19VIN, output filter components, parasitic inductance, and gate drive resistances were chosen to give realistic ripple current and voltage and accurate representation of the gate drive current capability. Circuit parasitic inductances were chosen for a “typical” 5x6mm PQFN layout. The essence of this paper is summarized in the next four plots. The plots summarize TCAD simulated MOSFET losses for the same high-side and low-side silicon die, altering circuit inductance to model the effects on high-side and low-side switching losses. The plots show MOSFET switching loss trends where, many times, even modest circuit inductance, due to careful layout and well-chosen packages yield total MOSFET losses that exceed the ideal or calculated expectations. Figure 14 provides a simplified version of the simulated TCAD circuit, which lumps many of the circuit inductances into MOSFET drain and source inductances, and is used to quantify the simulated circuit values for Figures 17-19.

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FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

B. Simulated Cases The four simulated cases describe the loss behavior for similar MOSFETs (FDMS8680x1 HS with FDMS8660ASx1 LS) operating around varying circuit inductances. Test conditions are: VIN = 19V, fSW = 300kHz, VOUT = 1.2V, VG = 5V. DEVICE

FDMS8692 FDMS8660AS

RDSON

QG(5)

QGD

QGS

RG

Vt

10VGS 4.5VGS (mΩ) (mΩ)

(nC)

(nC)

(nC)

(Ω)

(V)

8 30

2.1 5.2

2.7 12

1.0 1.2

1.8 1.7

Package

5x6 PQFN 5x6 PQFN

7.0 1.7

10.5 2.3

Case 1.) Zero Parasitic Inductance An initial simulation provides a baseline case for comparing losses. This case sets all parasitic inductance to zero value with MOSFET loss predictions summarized in Figure 16. MOSFET switching waveforms for this case resemble Figure 15 (zero parasitic inductance).

This case clearly demonstrates the necessity for low RDS(ON) for an optimized low-side switch as channel conduction losses dominate losses. It also shows that a well-designed high-side MOSFET can be optimized to equally distribute conduction and switching losses across load current, however, highside turn-on losses are nearly double turn-off due to diode QRR, which must be minimized. Case 2.) Typical 5x6mm PQFN Inductance Figure 17 resembles a “typical” DC-DC point-ofload (POL) circuit using packaged PQFN MOSFETs with well-designed (low inductance) power and gate loops. All parameters are identical to the circuit of Case 1, with the addition of parasitic inductance: Ls_HS=0.4nH, Ls_LS=0.4nH, Ld_HS=1.2nH, Ld_LS=0.3nH, Rg_HS=1Ω, Rg_LS=1Ω, Lg_HS=9nH, Lg_Ls=6.5nH.

2.5

0.5 0.0

25 amps

HS.drv

HS.Toff

HS.Ton

HS.Cond

LS.drv

7 amps

HS.Packg

Loss Mechanism

15 amps

LS.Swch

Iout ( A )

25 amps

1.0

LS.diode cond

HS.drv

HS.Toff

HS.Ton

HS.Cond

25 amps 20 amps 15 amps 10 amps 7 amps

HS.Packg

Loss Mechanism

LS.drv

LS.Cond LS.Packg LS.diode cond LS.Swch

LS.Loss HS.Loss

0.0

20 amps

LS.Cond

0.5

15 amps

1.5

LS.Packg

1.0

10 amps

2.0

LS.Loss HS.Loss

1.5

7 amps

Power Loss ( W )

Power Loss ( W )

2.5 7 amps 10 amps 15 amps 20 amps 25 amps

2.0

Iout ( A )

Fig. 16. MOSFET simulated loss - zero circuit inductance.

HS.Loss = total high-side silicon plus package loss LS.Loss = total low-side silicon plus package loss LS.Cond = low-side channel conduction loss LS.diode_cond = diode dead-time conduction loss LS.Packg = low-side package resistive loss LS.Swch = low-side loss associated with drain voltage and current during switching HS.Cond = high-side channel conduction loss HS.Toff = high-side turn-off switching loss due to the overlap of VDS and IDS HS.Ton = high-side turn-on switching loss due to the overlap of VDS and IDS HS.drv = high-side gate losses from QG(TOT) LS.drv = low-side gate losses from QG(TOT)

Fig. 17. MOSFET simulated loss - including circuit inductance (HS Lsource = 0.4nH).

The most notable loss difference from case 1 to case 2 is in the high-side MOSFET. Case 2 predicts close to 20% higher total high-side losses. Of that loss, turn-off losses have increased the most, due to added drain voltage stress from ringing and slower edges rates due to source inductance. This case describes the situation where only modest circuit inductance tends to shift higher losses towards the high-side turn-off transient, while lowering the turnon losses.

10

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

Case 3.) 5x6mm PQFN with Added High-Side Source Inductance Case 3 follows case 2, where an additional 0.4nH is added to Ls_HS (Ls_LS = 0.8nH versus 0.4nH). This case is typical of a situation where internal package bond wiring is not fully optimized, adding extra package inductance. 2.5 10 amps 15 amps 20 amps

1.5

25 amps

2.5

1.0

7 amps

0.5

HS.drv

HS.Toff

HS.Ton

HS.Cond

25 amps 20 amps 15 amps 10 amps 7 amps

HS.Packg

Loss Mechanism

LS.drv

0.0 LS.Swch

The additional package inductance for this case adds extra inductance in the high-current AC loop, as shown in Figure 20, which tends to slow switching. Moreover, the package inductance shows up as extra high-side common source inductance, which has strong effects on high-side losses. Common source inductance, often referred to as “source inductance,” is the inductance shared by both the gate and high-current loop, shown in Figure 20. It effects switching by generating a voltage between the MOSFET source and the gate drive return during drain current rise and fall. The source inductance voltage is actively (and negatively) fed back to the MOSFET VGS (measured at the silicon), slowing switching transients. High source inductance can significantly degrade MOSFET switching and is discussed in more detail in the following section. Comparing HS.Loss for Figure 18 versus 17, notice that the high-side losses are approximately 30% higher (1.6W vs. 1.2W). The extra loss is incurred by the high-side MOSFET in both the turnon and turn-off switching events, while low-side MOSFET switching losses actually decrease.

25 amps

1.0

LS.diode cond

Fig. 18. MOSFET simulated loss - including circuit inductance (HS Lsource = 0.8nH).

20 amps

LS.Cond

Iout ( A )

15 amps

1.5

LS.Packg

HS.drv

HS.Packg

HS.Toff

25 amps 20 amps 15 amps 10 amps 7 amps

HS.Ton

HS.Cond

LS.drv

LS.Swch

LS.diode cond

LS.Cond

Loss Mechanism

LS.Packg

LS.Loss HS.Loss

0.0

10 amps

2.0

LS.Loss HS.Loss

0.5

Power Loss ( W )

Power Loss ( W )

7 amps

2.0

Case 4.) 5x6mm PQFN with Added Low-Side Source Inductance The final case, shown in Figure 19, adds 0.4nH into the low-side source (Ls_LS = 0.8nH). This is common source inductance for the low-side (which actually helps hold the low-side gate off and is addressed in the shoot-through section of this paper), which adds additional loop inductance for added high-side losses. The trend is higher total losses with lower low-side losses and greater highside losses.

Iout ( A )

Fig. 19. MOSFET simulated loss - including circuit inductance (HS and LS Ls_LS = 0.8nH).

One clear trend is that increasing the power loop inductance, either through packaging or layout, severely impacts MOSFET power losses. The RDS(ON) x QG(TOT) FOM becomes less effective for selecting highly efficient MOSFETs for cases where high inductance completely dominates switching. C. High-Side Common Source Inductance Often, higher than expected losses in the highside switch arise from common source inductance, shown in Figure 20. As described, common source inductance (Ls_LS) is the inductance shared by both the gate loop and high-current AC loop. In general, for a control switch, the rapidly changing drain current (dIDS/dt) during MOSFET switching induces a source voltage (L x dIDS/dt) with a polarity always working against the gate drive action, i.e. negative feedback, shown in Figures 20 and 21. Both the MOSFET turn-on and turn-off currents are affected with slower switching speed, causing increased power losses. 11

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

LD_HS

Q1

LS_HS

92 90

Efficiency (%)

Figure 20 provides an example for the source inductance voltage generated during turn-off (i.e. falling drain current). L x di/dt

VIN

86 84

Lsource = 0.4nH

82

Lsource = 0.8nH

5

Q2

10

15

20

25

Iout (A) Fig. 22. Simulated efficiency for various high-side MOSFET source inductance cases.

RDRIVE_HS Ls_LS

High Current AC Loop

Gate Loop

Lsource = 2.3nH

78

LG_HS

LG_HS

Lsource = 1.2nH

80

Ld_LS RG_HS

88

An analysis of VGS and VDS switching waveforms displays the impact on switching times as the source inductance increases, as shown in Figure 23.

Fig. 20. Schematic with high-side MOSFET source inductance.

VDS_Si (LS_HS = 0.4 nH) (LS_HS = 2.3 nH)

27.5

7.0 6.0

20.0

4.0 5.0 VgsHS (V)

17.5 VdsHS (V) 12.5 15.0

3.0 2.0

10.0 7.5

1.0

5.0

0.0

7.0 2.0

2.5

3.82

3.83

3.84

3.85 -6 time (seconds) *10

3.86

3.87

3.88

3.89

0.0 -1.0

-2.5

0.0

2.5

1.0

-2.5

5.0

VGS

VGS_Si (LS_HS = 0.4 nH) (LS_HS = 2.3 nH)

-1.0

7.5

3.0

10.0

4.0 5.0 VgsHS (V)

VdsHSpac (V) 12.5 15.0

17.5

6.0

20.0

22.5

VDS

0.0

8.0

22.5

8.0

25.0

VgsHS

9.0

27.5

VgsHS

9.0

10.0

30.0

IdsHS

VDS and VGS (2V/div)

25.0

IDS

VdsHS VdsHSpac

VdsHSpac VgsHS

10.0

30.0

FDMS8680_FDMS8660AS_20A:0_0.1cycle.ivl

FDMS8680_FDMS8660AS_20A:0_0.1cycle.ivl

3.82

3.83

3.84

3.85 -6 time (seconds) *10

3.86

3.87

3.88

3.89

Time (10ns/div) Fig. 23. High-side MOSFET source inductance waveforms.

Fig. 21. Simulated high-side MOSFET waveforms for source inductance = 2.3nH.

The increased source inductance gives rise to a perceived increase in Miller time, shown in Figure 23 (0.4nH vs. 2.3nH). What is actually occurring is a trickle discharge of the gate voltage as the source inductance potential opposes the gate drive action. Figure 22 shows simulated efficiencies for varying high-side source inductance, where higher values (i.e. 2.3nH for D-Pak) show unacceptable performance for optimizing efficiency. The efficiency difference is over 5% points at full load versus 0.4nH (PQFN). For this simulation, VIN=19V, VOUT=1.3V, and fS = 300kHz.

The plot provides a comparison of the high-side gate and drain voltage waveforms, comparing conditions where Ls_HS=0.4nH vs. 2.3nH with the same silicon. Identifying high source inductance through lab measurement can be accomplished through VGS and VDS oscilloscope measurements using high bandwidth probes (500MHz). However, many times, the measured waveforms from packages, such as the D-Pak or PQFN, do not allow for clear measurements across the MOSFET silicon since packaging parasitic inductance is also measured. Figure 24 provides a simulated example showing the VGS measurement at the package gate-source pins compared to the much different VGS measured at the MOSFET die. Care must be exercised when interpreting the lab-measured waveforms. 12

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009 Q1

LS_HSpack

RG_HS

VGS_si LG_HSpack

VGS_pkg LG_HSbrd RDRIVE_HS

FDMS8680_FDMS8660AS_Ls1nH_20A:0_0.1cycle.ivl

10.0

30.0

VdsHS VgsHS

9.0

27.5

VgsHSpac

7.0 6.0

20.0

4.0 5.0 VgsHS (V)

17.5 VdsHS (V) 12.5 15.0

3.0

10.0

VGS_Si

2.0

-2.5

0.0

0.0

2.5

1.0

5.0

7.5

VGS_pkg

VGS ( 1 V/div)

VDS ( 2.5 V/div)

22.5

8.0

25.0

VDS

3.810

3.815

3.820

3.825

3.830

3.835 3.840 -6 time (seconds) *10

3.845

3.850

3.855

3.860

3.865

Time (5ns/div) Fig. 24. High-side MOSFET source inductance measurement.

D. Dead Times 1) High-Side Off to Low-Side On The high-side off to low-side on transition is typically free of issues like cross-conduction, however, the goal should be to minimize the body diode conduction time, allowing enough time for the phase node to drop below ground potential (lowside body clamps this node to approximately -0.6V) before releasing the low-side gate drive to turn on the MOSFET channel. This ensures crossconduction is eliminated since the gate driver does not respond until body diode conduction has been initiated. This technique is typically used for synchronous buck (or half-bridge)-type gate drivers that utilize anti-cross-conduction circuitry. From Figure 12, this is approximately time (t4 - t2). 2) Low-Side Off to High-Side On Switching Transition (Break-before-Make) The low-side off to high-side on transition is usually the switching event that requires the most attention when selecting a compatible MOSFET for

a given gate driver. This is also the switching event that can be the most problematic when dealing with optimizing efficiency. The goal of this transition is to quickly switch current from the channel to the body diode, which must be minimized to optimize losses, yet long enough to prevent cross-conducting currents from allowing the high- and low-side MOSFET channels from conducting simultaneously. This is also when both diode QRR and any potential [CGD x dVDS/dt] induced shootthrough currents occur. All of these conditions require special care in selecting a low-side MOSFET. This event begins when the low-side gate drive pulls low, providing a low resistance path discharging the low-side MOSFET gate-to-source voltage shifting current from the MOSFET channel to the body diode. After another short delay, the gate of the high-side MOSFET is charged, initiating turn-on. The more popular synchronous buck gate drivers typically utilize an adaptive gating procedure where the low-side off to high-side on transition are performed by monitoring the low-side gate-tosource signal until a preset threshold level (~ 1V) is reached. After a short delay (from Figure 13, t10 – t8) the high-side gate driver is released to charge the high-side MOSFET. This type of gating attempts to ensure that any low-side logic-level MOSFET used has fully turned off the channel before the high-side MOSFET is gated on, since the gate drive is monitoring the gate signal. a) Diode QRR The diode reverse recovery time (tRR) and reverse recovery charge (QRR) specified on datasheets are generally used by loss calculators as straightforward (QRR x fSW x VIN) switching losses. A word of caution on using datasheet QRR numbers for loss calculations: The reverse recovery current of a diode is a function of many parameters, such as forward current IF, reverse recovery diF/dt, DC bus voltage, and junction temperature TJ. An increase in any one of these conditions generally results in increased QRR. Datasheet test conditions are usually lower than typical converter operating conditions. The low test conditions typically arise for manufacturing test reasons (i.e. TJ=25°C, IF=1A, dIF/dt=100A/µs). 13

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

Since switching converters try to switch the MOSFET as fast as possible, edge rates, such as diF/dt, can be up to ten to twenty times faster than the datasheet test conditions, increasing diode QRR for DC-DC. To further complicate the issue, diode recovery times and charge reported on datasheets are often the sum of COSS displacement current and the recovered minority carrier current, QRR, and the reactive currents arising from test circuit loop inductance and capacitance, as shown in Figure 25. As a result, the “QRR” number reported on the datasheet is heavily dependent on the influence of currents arising from a non-ideal testing environment. Test circuits tend to have higher inductance values compared to a well-designed DCDC PCB, since accommodations are made for current sensing and test sockets. dIF/dt

tA phase w/ inductance

tA phase

tB phase w/ inductance

tB phase

ISD(Q2)

VDS(Q2)

tB3

tB

QRR showing QOSS contribution

A common method to reduce both QRR (and diode conduction losses) is the insertion of a Schottky diode placed in parallel to the body diode. This technique, while solid in theory, rarely gives the optimal benefit of reducing both conduction and QRR losses because the diode is physically separated from the body diode with parasitic package and wiring inductance. Moreover, gains in efficiency quickly diminish as dead times reduce, since the Schottky diode becomes less efficient at transferring load current. b) SyncFET MOSFET The most efficient method of minimizing QRRrelated switching losses is with a monolithically integrated Schottky diode on the low-side MOSFET die (SyncFET MOSFET). This can be one of the most important features added to the low-side MOSFET. A well-designed Schottky diode features decreased dead-time diode conduction losses, dramatically reduced switching losses attributed to QRR, softened diode recovery resulting in lower drain voltage stress and ring energy, and additional output capacitance (COSS), further reducing the recovery dVDS/dt and aiding the prevention of C x dVDS/dt turn-on. In many circuits, the SyncFET MOSFET provides much higher efficiencies at lighter loads where QRR related losses dominate total losses, as shown in Figure 26.

QRR with circuit inductance tA1 tA2 tA3

Fig. 25. Diode QRR showing COSS displacement current.

While there are many factors to consider when using datasheet QRR for MOSFET loss estimates, TCAD simulations show that the combined effect from diode QRR plus the stored energy from the parasitic loop inductance generally equates to a perceived two-to-three-times increase in QRR (from reactive currents) when used in a typical DC-DC converter, as simulated in Figure 14. This increase is compared to an in-house QRR test circuit. A conservative estimate for QRR losses typically takes into account the ½LI2 losses from loop inductance.

14

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009 HS.Packg 0.7%

HS.drv 1.9%

HS.Ton 6.7%

IOUT = 10A

LS.Cond 20.5%

HS.Toff 8.5% LS.Packg 5.2%

HS.Cond 6.6%

LS.diode cond 3.4%

LS.drv 4.6% LS.Swch 42.1%

HS.Packg 1.4%

HS.drv 0.5%

HS.Ton 10.0%

IOUT = 25A

HS.Toff 11.8%

LS.Cond 37.5%

Typically, a “shoot-through” condition arises from capacitive feedback current through CGD into CGS inducing a gate-bounce-induced channel turn-on of the synchronous MOSFET, as shown in Figures 27 and 28. Holding the gate below threshold is challenging because the high-frequency capacitive displacement current from CGD (due to dVDS/dt) couples back to circuit ground through the gate electrode. The gate-to-ground impedance is the parallel combination of the gate drive (ZG_DRV) and the MOSFET gate-to-source (ZMOS_Gate) paths. As dVDS/dt increases, the more favorable path for displacement current is through the capacitive gatesource (CGS) path versus the highly inductive and resistive gate drive loop.

HS.Cond 12.9%

LS.drv 1.3%

Ld_LS

LS.Packg LS.Swch LS.diode cond 10.5% 9.2% 4.9%

RDRIVE_LS

LG_brd LG_pack RG

CGD

CGS

Fig. 26. TCAD simulated switching loss. ZGate_Drv ~ R + ωL

Another advantage of the SyncFET MOSFET is that the monolithic nature of the Schottky diode cell creates a high-frequency path from the MOSFET channel to Schottky diode, which essentially guarantees the PN body diode never completely turns on (at reasonable currents). This situation is much different from the case where an external Schottky diode is placed in parallel to the MOSFET body diode through an inductive loop created from packaging and layout inductance. With the SyncFET MOSFET, the reduction in QRR is accomplished by adding Schottky diode area into the MOSFET by an amount much smaller in area than the discrete Schottky diode. Moreover, reduced switching losses from the SyncFET MOSFET can also be balanced with a higher RDS(ON) MOSFET to achieve very high light-to mid-load efficiency while still attaining similar heavy-load converter efficiency compared to a non-SyncFET MOSFET. c)

Shoot-Through and Cross-Conduction Another common loss encountered in high-speed DC-DC circuits is an unwanted CGD x dVDS/dt (C x dv/dt) induced turn-on of the channel[15][16].

ZMOS_Gate ~ 1/ωC

Q2 Ls_LS

Fig. 27. Synchronous rectifier switching waveforms showing [C x dv/dt] induced turn-on.

Often, the most notable feature about C x dv/dt turn-on is the changing (shallower) slope of the drain voltage waveform as the channel turns on. It is rarely a destructive event and more of a nuisance causing increased power losses. The event is also self-limiting since, as the channel turns on, dVDS/dt decreases, which allows for the gate voltage to discharge slowly, turning the channel back off. C x dv/dt induced turn-on is encountered frequently in synchronous buck designs and can actually aid in limiting VDS stress during diode recovery when parasitic inductance is included. However, it is typically recommended to design a PCB and select compatible MOSFETS / gate drivers to avoid shootthrough for maximum performance. It is strongly recommended to select a MOSFET with low internal gate resistance (RG) and lay out a PCB with low gate loop inductance to maximize low-side gate drive peak current capability, which 15

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

minimizes gate bounce and shoot-through currents. Using MOSFETs with low QGD/QGS ensures that shoot-through is minimized. Selecting low-QGD/QGS MOSFETs provides minimizing gate bounce since the total charge delivered to CGS from CGD results in a lower gate bounce for a given gate impedance. Low Side Channel Turn-On

the preset threshold (~1V), while the MOSFET VGS is at a much higher potential, where the channel is still gated on. Unlike C x dv/dt induced turn-on, cross-conduction due to gate overlap can cause excessive power dissipation that can damage the MOSFETs. This is a situation that must be avoided to attain high manufacturing reliability.

VGS(Q1)

VGS(Q1)

Ld_LS CGD

VDS(Q2)

VDS(Q2)

ZG CGS

VGS(Q2)

VDRV

Q2

VGS(Q2)

VGS

1V VDRV

Ls_LS

VGS(Q2) w/ Lsource

Fig. 29. Cross-conduction.

VgsHS

30.0

30.0

VdsLS

VdsLS

18.0

27.5

VgsLS 18.0

27.5

VgsLS

16.0

25.0

3.580

3.585

3.590

3.595

3.600 3.605 -6 time (seconds) *10

3.610

3.615

3.620

3.625

3.630

8.0 10.0 VgsHS (V) 6.0 2.0 0.0 -2.0

0.0 -2.5

2.5

0.0 -2.0

2.0

5.0

4.0

7.5 4.0

7.5

VGS(HS) VGS(LS) 3.575

14.0 12.0

20.0 17.5 VdsLS (V) 12.5 15.0 10.0

8.0 10.0 VgsHS (V)

VGS(HS) VGS(LS)

6.0

10.0

VdsLS (V) 12.5 15.0

17.5

12.0

20.0

14.0

22.5

16.0

25.0

VDS(Pk) = 29V VDS(Pk) = 24V

22.5

20.0

FDMS8680_FDMS8660AS_Ls0p1_20A:0_0.1cycle.ivl VgsHS

20.0

FDMS8680_FDMS8660AS_Ls1nH_20A:0_0.1cycle.ivl

5.0

Another approach to eliminate gate bounce is to consider the low-side source inductance[10], which can aid in preventing C x dv/dt shoot-through. During high turn-on (low-side diode recovery dIF/dt), the L x dIDS/dt voltage generated across Ls_LS actually drives the low-side MOSFET source node positive with respect to ground, which acts to charge VGS negative, as shown in Figure 27. Driving the gate negative allows added headroom for gate bounce since the ∆VGS from C x dv/dt is applied to a negative gate potential. A shoot-through or “cross-conducting” situation can also arise when an overlap of gate signals causes both MOSFETs to simultaneously conduct, as seen in Figure 29. Since adaptive dead-time algorithms are usually used, cross-conduction generally arises due to a layout-related issue or an interaction with a MOSFET parameter, such as RG. Figure 29 depicts a common situation where both RG and LG (impedance ZG) cause the MOSFET gate-to-source signal to differ dramatically from the gate driver signal, causing errors in [15] measurement . This typically reduces the dead time since the gate drive is sensing a voltage below

2.5

Fig. 28. Synchronous rectifier switching waveforms showing [C x dVDS/dt] induced turn-on.

Figure 30 compares TCAD simulated shootthrough to cross-conduction for the same MOSFETs and circuit inductance from Figure 15, where the difference is the dead time.

0.0

t0 tA tB

-2.5

IDS

3.55

3.56

3.57

3.58

3.59 -6 time (seconds) *10

3.60

3.61

3.62

3.63

Fig. 30. TCAD simulated synchronous rectifier switching waveforms showing cross-conduction vs. dv/dt induced shoot-through.

The plot shows that the two events are much different in nature, where the cross-conduction often times can allow a very large cross-conducting current to create a large drain voltage overshoot. It also limits dv/dt, as the switching is slowed due to the simultaneous high-side and low-side MOSFET conduction. In contrast, C x dv/dt typically has a fast initial dv/dt, but tends to limit the peak VDS as the channel turns on.

16

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

A. Die Size vs. Efficiency Generally, in a low-inductance circuit with low packaged inductance power MOSFETs, the RDS(ON) x QG(TOT) (QGD) FOM set certain expectations and trends for efficiencies. For example, it is common knowledge that a control MOSFET needs to be optimized for both switching and conduction losses if high converter efficiency is desired. It should also be expected (from loss equations) that, for a family of die sizes (for a given FOM silicon technology in similar packages), an optimal die size exists where efficiencies can be maximized across the useable load current range. This reasoning holds for both high- and low-side MOSFET selections. 1) High-Side Die Size for 12VIN and 19VIN V-Core Figure 31 provides a comparison of 3x3mm PQFN high-side MOSFETs for efficiency at 12VIN and 19VIN. The test platform is a dual-phase 300kHz operating notebook V-Core regulator. Part names with typical specifications are listed below. For 12VIN, as expected, the smaller lower QG(TOT) MOSFET (FDMC8296) excels at lighter load efficiency where switching losses dominate, while the lower RDS(ON) (FDMC8676) becomes more efficient at heavier loads where RDS(ON) losses dominate. At 19VIN, where high-side switching losses can be very large, the FDMC8296 gives higher efficiency across the load current range.

DEVICE

FDMC8676 FDMC8296

RDSON

QG(5) QGD QGS

RG

Vt

10VGS 4.5VGS (mΩ) (mΩ)

(nC) (nC) (nC)

(Ω)

(V)

10 7.6

0.8 0.9

1.8 1.9

Package

3x3 PQFN 3x3 PQFN

4.7 6.5

7.1 9.5

3 3

4 2.5

91

Efficiency (%)

87

83

FDMC8296 - FDMS8660AS - 12Vin FDMC8676 - FDMS8660AS - 12Vin

79

FDMC8296 - FDMS8660AS - 19Vin FDMC8676 - FDMS8660AS -19Vin

75

0

10

20

30

40

50

Iout (A)

Fig. 31. Efficiency with varying die-size high-side MOSFETs; two-phase notebook V-Core [VIN=12&19V, VOUT=1.3V, fSW=300kHz, VG=5V, L=0.56µH, HS RDRV (source / sink = 0.8Ω Ω ), LS RDRV (sink = 0.5Ω Ω / source = 1.0Ω Ω )].

2) Low Side Die Size for 19VIN V-Core A similar efficiency versus IOUT trade-off exists for the low-side MOSFET die size shown in Figure 32. This case shows the smaller die, higher RDS(ON) MOSFETs reduce switching losses at lower currents due to lower QRR and QG(TOT), but become less efficient at higher currents compared to larger die as RDS(ON) losses dominate. The test platform is a single-phase point of load (POL). RDSON

QG(5) QGD QGS

RG

10VGS 4.5VGS (mΩ) (mΩ)

(nC) (nC) (nC)

(Ω)

(V)

1.0 1.4 1.1

1.5 1.5 1.5

DEVICE

FDMS8660S FDMS8670S FDMS8672S

5x6 PQFN 5x6 PQFN 5x6 PQFN

1.9 2.8 4.0

2.6 3.6 5.2

44 24 16

16 10 6

11 8 5

Vt

90

Efficiency (%)

VI. EFFICIENCY MEASUREMENTS This section provides and reviews measured efficiency curves covering many of the topics discussed throughout this paper. The examples encompass many synchronous buck applications from 12V input desktop computer voltage core (VCore) regulators (D-PAK MOSFETs) to 19.5VIN Notebook V-Core with both SO-8 and PQFN MOSFETs to generic synchronous buck POLs. Many of the effects are studied with the aid of measured switching waveforms to determine efficiency trends. Cases reviewed are: A.) die size versus efficiency, B.) packaging effects, C.) C x dv/dt induced shoot-through, D.) cross-conduction between high- and low-side MOSFETs, E.) SyncFET MOSFET versus externally placed Schottky diode.

85

FDMS8680 - FDMS8660S - 19Vin 80

FDMS8680 - FDMS8670S - 19Vin FDMS8680 - FDMS8672S - 19Vin

75 0

5

10

15

20

25

Iout (A)

Fig. 32. Efficiency with varying die-size low side MOSFETs; single-phase POL - [VIN=19V, VOUT=1.3V, fSW=500kHz, VG=5V, HS RDRV (pull up / down = 1Ω Ω ), LS RDRV (pull down = 0.5Ω Ω / pull up = 1Ω Ω )].

Typically, when trends such as these exist, the power MOSFETs are operating as expected, where gate drive and MOSFET RG / CISS time constants 17

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

are dictating the switching behavior. However, these trends change quickly when very low impedance gate drivers are used in combination with slight increases in source inductance. B. Packaging Effects As noted throughout this paper, high packaging parasitics combined with a less than ideal layout can degrade (or severely degrade) the converter efficiency. A few cases presented below compare various packaging technologies and their influence on efficiencies. 1) 5mm x 6mm PQFN High-Side vs. Die Size Selecting a high-side MOSFET for optimized efficiency usually requires a brute-force method of narrowing down enhanced FOM MOSFETs combined with a considerable amount of lab data. This brute-force method is a common technique since, more often than not, datasheet parameters and FOM don’t fully correlate with lab data. One reason for unexpected efficiency trends or lower efficiency is package inductance and at times, very modest inductance. DEVICE

FDMS8692 FDMS8680

RDSON

QG(5) QGD QGS

RG

Vt

10VGS 4.5VGS (mΩ) (mΩ)

(nC) (nC) (nC)

(Ω)

(V)

1.0 0.8

1.8 1.8

Package

5x6 PQFN 5x6 PQFN

7.0 5.5

10.5 8.5

8 10

2.1 2.7

2.7 3.2

Efficiency (%)

91

advantage across the entire load current range for the FDMS8680, which seems to contradict the example shown in Figure 30. What should be noted here is that random selection of MOSFETs can yield unexpected efficiency trends as manufacturing tolerances are factored in (i.e MOSFET FOM has variance influencing efficiency data). For this test case, efficiency trends were verified over numerous testing of random MOSFET date codes. The reason behind the increased efficiency is package inductance. The larger die FDMS8680 is constructed with slightly lower package inductance, giving rise to lower switching losses. 2) 3mm x 3mm vs. 5mm x 6mm PQFN High Side The 3mm x 3mm PQFN has quickly emerged as an excellent contender for high-efficiency high-side MOSFET in high-current (>25A) POLs. 30V BVDSS rated trench MOSFETs have pushed the typical 10VGS RDS(ON) of the packaged device to 4mΩ and will continue to achieve unprecedented onresistance in the near future, where a single 3x3mm packaged device begins to realize high-current operation when used as a synchronous rectifier. Efficiency curves in Figure 34 compare similar MOSFET die packaged in both 3x3mm PQFN (FDMC8296) and 5x6mm PQFN (FDMS8692 – used in previous example), using the same low-side MOSFET. The MOSFET parameters are shown below.

87

DEVICE

83

FDMS8692 FDMC8296

FDMS8680 - FDMS8660AS - 12Vin

Package

5x6 PQFN 3x3 PQFN

RDSON

QG(5) QGD QGS

RG

10VGS 4.5VGS (mΩ) (mΩ)

(nC) (nC) (nC)

(Ω)

(V)

8 7.6

1.0 0.9

1.8 1.9

7.0 6.5

10.5 9.5

2.1 2.5

2.7 3

Vt

FDMS8692 - FDMS8660AS - 12Vin

79

FDMS8680 - FDMS8660AS - 19Vin FDMS8692 - FDMS8660AS - 19Vin

75 0

10

20

30

40

50

Iout (A)

Fig. 33. 5mm x 6mm versus 3mm x 3mm high-side comparison; twophase notebook V-Core [VIN=12&19V, VOUT=1.3V, fSW=300kHz, VG=5V, L=0.56µH, HS RDRV (source / sink = 0.8Ω Ω ), LS RDRV (sink = 0.5Ω Ω / source = 1.0Ω Ω )]

Again, this efficiency trend indicates that circuit inductance is beginning to influence switching. For this comparison, the benefit of the FDMC8296 (3x3mm) over the FDMS8692 (5x6mm) is a combination of enhanced package inductance and resistance, which works together to increase efficiency across the entire load current.

Figure 32 provides an efficiency example comparing two high-side MOSFETs of similar silicon technology (FDMS8680 vs 8692) scaled for die size and packaged in a 5mm x 6mm PQFN. The curve shows a clear and distinct efficiency 18

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009 90

91

83

Efficiency ( % )

FDMC8296 - FDMS8660AS - 12Vin

85

FDD6296x1 HS, FDD8896x2 LS 80

FDMS8690x1 HS, FDD8896x2 LS

FDMS8692 - FDMS8660AS - 12Vin

79

FDD8880x1 HS, FDD8896x2 LS

FDMC8296 - FDMS8660AS - 19Vin

75

FDMS8692 - FDMS8660AS - 19Vin

0

75

10

20

30

40

50

60

70

80

Iout ( amps )

20

30

40

50

Iout (A)

Fig. 34. 5mm x 6mm high-side die size comparison; two-phase notebook V-Core [VIN=12&19V, VOUT=1.3V, fSW=300kHz, VG=5V, L=0.56µH, HS RDRV (source / sink = 0.8Ω Ω ), LS RDRV (sink = 0.5Ω Ω / source = 1.0Ω Ω )]

It is worth noting that the FDMC8296 (3x3mm PQFN) rivals the larger FDMS8680 (5x6mm PQFN in Figure 32) for efficiency. This is a very compelling advantage for converter designers wishing to simultaneously increase power density with efficiency.

DEVICE

Package

RDSON 10VGS 4.5VGS (mΩ) (mΩ)

FDD8880 FDD6296 FDMS8690

D-PAK D-PAK 5x6 MLP

7.0 7.0 7.4

9 9 9.9

QG(5) QGD QGS

RG

Vt

C. CGD x dVDS/dt Shoot-Through Shoot-through arising from CGD x dVDS/dt induced turn-on is one of the most common reasons for decreased efficiency, especially at lighter load currents. Waveform measurement of the low-side gate and drain are typically the easiest method to check for shoot-through[15], as shown in Figure 36. Low Side Vds during diode recovery Comparison waveforms of C dVds/dt induced shoot through versus no C dVds/dt. 35

7

VDS with C dv/dt VDS without C dv/dt Vds high Qgd device - C dv/dt shoot thru

30

6

Vds typical device - no C dv/dt shoot thru Vgs high Qgd device - C dv/dt shoot thru

Vgs typical device - no C dv/dt shoot thru

25

5

20

4

15

3

10

2

5

1

0

0

-5

-1

-10 20

40

60

80

100

time ( nsec )

(nC) (nC) (nC)

(Ω)

(V)

13 5 12.2 3.5 10 2.9

1.3 1.1

1.7 1.6

3.8 4 3.5

While the enhanced FOM FDD6296 outperforms the higher gate charge FDD8880, the advantage goes to the lower inductance MLP (FDMS8690).

VGS (1V/div)

3) D-PAK vs. PQFN Figures 33 and 34 describe cases where mild package parasitics modestly influence MOSFET switching. When dealing with packages such as the D-PAK, the inductive influence on switching behavior can be severe. Figure 35 shows an example comparing efficiencies when using two different FOM D-PAK high-side devices along with a comparison to 5x6mm MLP.

Fig. 35. D-PAK vs. MLP high-side efficiency; [VIN=12V, VOUT=1.3V, fSW=300kHz, VG=12V, RDRV HS (pull up / down = 3.8Ω Ω / 1.4Ω Ω ), RDRV LS (pull up / down = 3.4Ω Ω / 1.4Ω Ω )]

Vds ( volts )

10

VDS (5V/div)

0

Vgs ( volts )

Efficiency (%)

87

VGS with C dv/dt VGS without C dv/dt 120

-2 140

Time ( 20ns/div) Fig. 36. Low-side switching waveforms for C x dv/dt

The waveforms of Figure 36 combined with an efficiency test from similar FOM low die MOSFETs with varying RDS(ON) (scaled die sizes) provides for a clear picture of the problem, as shown in Figure 37. The curves show a seven-point efficiency difference for the FDMS8660S to the FDMS8672S at 7A output current, which is a sign of excessive switching losses. This situation typically indicates that the layout and driver are not working well with the selected MOSFETs.

19

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009 RDSON

QG(5) QGD QGS

RG

Vt

10VGS 4.5VGS (mΩ) (mΩ)

(nC) (nC) (nC)

(Ω)

(V)

1.0 1.4 1.1

1.5 1.5 1.5

DEVICE

FDMS8660S FDMS8670S FDMS8672S

5x6 PQFN 5x6 PQFN 5x6 PQFN

1.9 2.8 4.0

2.6 3.6 5.2

44 24 16

16 10 6

11 8 5

90

Efficiency [%]

85

80 FDMS8680 +FDMS8660S

75

to the gate loop layout. Specifically, oversized wide gate traces and small gate loop area for minimizing gate inductance, along with low MOSFET RG, are recommended for the low-side MOSFET. Figure 39 is an efficiency comparison depicting a cross-conducting situation. This example presents two low-side SyncFET MOSFETs that are diescaled for size. In this example, the FDS6699S (larger die) shows a much lower than expected efficiency, while the FDS6688S (smaller die) performs well.

FDMS8680 +FDMS8670S

90 90

FDMS8680 +FDMS8672S

5

10 15 Load Current [A]

20

25

Fig. 37. Efficiency with higher QGD low-side MOSFETs; one-phase POL [VIN=19V, VOUT=1.3V, fSW=500kHz, VG=5V, L=0.22µH, HS RDRV (pull up /down=1Ω Ω ), LS RDRV(pull down/up=0.5Ω Ω /1Ω Ω )]

For this example, it is recommended to use MOSFETs with lower QGD (or QGD/QGS), which can alleviate the problem shown in Figure 38. DEVICE

FDMS8660AS FDMS8670AS FDMS8672AS

Package

5x6 PQFN 5x6 PQFN 5x6 PQFN

RDSON

QG(5) QGD QGS

RG

Vt

10VGS 4.5VGS (mΩ) (mΩ)

(nC) (nC) (nC)

(Ω)

(V)

1.2 0.9 0.8

1.7 1.7 1.8

1.7 2.4 4.0

2.3 3.5 5.2

30 20 15

5.2 4 3.4

12 7.2 5.6

Efficiency [%]

85

80 FDMS8680 +FDMS8660AS FDMS8680 +FDMS8670AS FDMS8680 +FDMS8672AS 70 0

5

10 15 Load Current [A]

20

80 80

I

FDS6294x2 HS, FDS6688Sx2 LS FDS6294x2 – FDS6688Sx2 FDS6294x2 – FDS6699Sx2 FDS6294x2 HS, FDS6699Sx2 LS

75 75 70 70 0 0

(A)

5

10

15

20

25

30

5

10

15

20

25

30

Fig. 39. Efficiency comparison (cross-conduction); [VIN=19V, VOUT=1.3V, fSW=300kHz, VG=5V, L=0.7µH, RDRV HS (pull up / down = 1.0Ω Ω , RDRV LS pull down= 0.5Ω Ω / pull up= 1Ω Ω )]

90

75

85 85 Efficiency ( % )

0

Efficiency (%)

70

25

Fig. 38. - Efficiency with lower QGD low-side MOSFETs; one-phase POL [VIN=19V, VOUT=1.3V, fSW=500kHz, VG=5V, L=0.22µH, HS RDRV (pull up /down=1Ω Ω ), LS RDRV (pull down/up=0.5Ω Ω /1Ω Ω )]

D. Cross-Conduction Cross-conduction typically creates a clear and distinct overlap in high-side and low-side gate voltages. Since most popular gate drivers use an adaptive dead time, this is often considered a nonissue. However, as many datasheets and application notes point out; for the gate drive adaptive dead time to operate correctly, attention needs to be paid

The first step in diagnosing the problem is to measure low-side VDS and VGS waveforms. These two waveforms contain enough information to reveal whether the problem is C x dv/dt or crossconduction related. For this example, the measured waveforms of Figure 40 show the limited (near nonexistent) body diode conduction, which is a signal of high- and low-side gate overlap. For the body diode measurement, the low-side VDS (or phase node) waveform requires a zoom-in on the region of interest (body diode conduction). The gate driver used has an adaptive dead time of 20ns, which should yield distinct (and intended) diode conduction shown in Figure 41 (same gate driver used in combination with a low impedance gate loop layout).

20

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009 Fig. 42. Body diode conduction for FDS6688S vs. FDS6699S.

FDS6699S

diode beginning conduction VGS = 1V/div, VDS = 5V/div

VGS = 1V/div, VDS = 0.1V/div

One of the common reasons for cross-conduction arises from MOSFET RG in combination with high gate loop inductance from layout (as is the case for the efficiency curve, see Figure 39). This situation causes dramatic signal differences from the low-side MOSFET VGS versus the low-side drive-to-ground voltage, shown in Figure 43.

Time (10 ns/div) Fig. 40. Zoom of VDS for body diode voltage.

The diode conduction of the FDS6688S, shown in Figure 42, is still not in the full body diode conduction stage (channel partially on), but the channel current is low enough to nearly prevent cross-conduction. This is a situation where any cross-conduction currents would be equal to or less than diode related losses (VF and QRR). It is important to note that any changes in MOSFET or driver parameters can cause dramatic changes in efficiency. In addition, operating on the edge of crossconduction can be desirable for eliminating diode related losses, but typically requires a more advanced anti-cross-conduction algorithm. VGS = 1V/div, VDS = 0.1V/div VIN = 19V VOUT = 1.2V IOUT = 15A L = 0.45µH

Diode conduction

Time (10 ns/div) Fig. 41. - MOSFET with ample diode conduction. VGS = 1V/div, VDS = 0.1V/div

FDS6688S

FDS6699S

Low-side driver voltage measured at package pins (1V/div)

VGS measured at package pins (1V/div)

LS FET VDS (zoom) 1V/div

HS FET VGS (1V/div)

Time (10 ns/div) Fig. 43. MOSFET VGS vs. LS gate drive signal.

The severe differences in signals can “trick” the low-side gate anti-cross-conduction circuitry into detecting the low-side MOSFET gate as below the preset threshold of (~1V), basically defeating the adaptive nature of the circuit. E. SyncFET MOSFET SyncFET MOSFET devices have been very successful in power-sensitive applications, such as computer notebooks and server regulators. High efficiencies at light and mid loads are becoming increasingly important as designs strive to increase battery life, while also meeting Energy Star requirements[17]. The advantages of SyncFET MOSFETs are increased efficiency across the usable load current range, while using a lower component count and decreased switch-node ringing, as shown in Figure 44. Figure 45 is useful for comparing efficiencies of the SyncFET MOSFET (FDS6299S) to an equivalent non-SyncFET MOSFET (FDS6299) with and without an external Schottky diode. The SyncFET MOSFET advantage is clear (dead times ~ 20ns).

Time (10 ns/div) 21

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009 90

Efficiency (%)

VSW-NODE with SyncFET

85

FDS6694x1 HS, FDS6688Sx2 LS FDS6694x1 HS, FDS6688x2 LS2 LS

80 0

5

10 15 Iout (amps)

20

25

Fig. 46. SyncFET vs. non-SyncFET comparison; [VIN=12V, VOUT=1.5V, fSW=300kHz, VG=5V, L=1µH, RDRV HS (pull up / down = 1.5Ω Ω , RDRV LS pull down = 1Ω Ω / pull up = 1.5Ω Ω )]. Fig. 44. SyncFET impact on switch node voltage.

Efficiency ( % )

90

FDS6298x1 HS, FDS6299Sx1 LS

88 86 84

FDS6298x1 HS,FDS6299 eqvlnt. LS no ext Schottky

82

FDS6298x1 HS, FDS6299 eqvlnt. LS with ext Schottky

80 78 0

5

10

15

20

IOUT ( Amps ) Fig. 45. SyncFET vs. external Schottky; one-phase POL - [VIN=19V, VOUT=1.3V, fSW=340kHz, VG=5V, L=0.7µH, HS RDRV (pull up / down = 1Ω Ω ), LS RDRV (pull down / up = 0.5Ω Ω / 1Ω Ω )].

While higher VIN (19.5V) battery applications are known to highlight the SyncFET MOSFET advantages, the actual benefit of the SyncFET MOSFET is seen across many 12VIN (and even 5VIN) generic Point-of-Load (POL) converters. Figure 46 provides an example comparing the FDS6688 (non-SyncFET MOSFET) to the FDS6688S (SyncFET MOSFET) in a generic 12VIN POL. In this example, the efficiency gains actually outweigh the previous 19VIN application. These situations occur because the QRR-related switching losses are a strong function of layout and gate drive impedance.

VII. CONCLUSION Power MOSFETs used as DC-DC converter switches are often selected based on the RDS(ON) x QG(TOT) (or QGD) FOM. Enhanced FOM typically correlates well with high efficiency due to fast switching control switches and high dVDS/dt immunity for synchronous switches. While this FOM combined with RG, QRR, and VTH (VPLATEAU) provides insight into MOSFET performance, calculated losses solely associated with these parameters typically underestimate measured MOSFET losses. Additional switching losses often arise from parasitic package or PCB layout inductance. Excessive common-source inductance is often encountered. This can significantly increase control switch losses, slow switching speeds, and increase voltage stresses during transients. For modern MOSFETs with a low FOM, a reduction in source inductance from (0.8nH to 0.4nH) results in a onepercentage improvement in efficiency at 25A. In power-sensitive converters, care should be taken in choosing low-inductance packages, such as PQFN and MLP over packages such as the TO-252 (D-PAK). Parasitic inductance also increases voltage and current stresses that can translate into the need for higher BVDSS-rated MOSFETs with a poorer Figure of Merit. To combat these stresses and allow for the lowest possible BVDSS, additional MOSFET features, such as the integrated Schottky diode in the SyncFET MOSFET, alleviate the voltage and current stresses, while providing enhanced performance. 22

FAIRCHILD SEMICONDUCTOR POWER SEMINAR 2008 - 2009

REFERENCES [1] [2] [3] [4] [5] [6] [7]

[8] [9] [10] [11] [12] [13]

[14]

[15] [16]

[17]

J. Klein, “Synchronous Buck MOSFET Loss Calculator with Excel Model”, AN-6005, Fairchild Semiconductor. ISL6227 Datasheet, Intersil, August 2007. IRF7832 Datasheet, International Rectifier, June 2005. Alan Elbanhawy, “Segmented Voltage Regulator Modules (VRM) as a solution for CPU Core Voltage, AN-7018, Fairchild Semiconductor. Alan Elbanhawy, “The Road to 200 Ampere VRM”, AN-7016, Fairchild Semiconductor. FDD8880 PSPICE Model, Fairchild Semiconductor, May 2003. Mark Pavier, Andrew Sawle, Arthur Woodworth, Ralph Monteiro, Jason Chiu, Carl Blake, “High-Frequency DC:DC Conversion : The Influence of Package Parasitics”, Proc. APEC 2003. Dan Calafut, “Trench Power MOSFET Low-Side Switch with Optimized Integrated Schottky Diode SyncFET”, proc. ISPSD 2004. Brian Lynch and Kurt Hesse, “Under the Hood of Low-Voltage DC/DC Converters” ,Texas Instruments 2002 Power Supply Design Seminar. Donald Schelle and Jorge Castorena, “Buck-Converter Design Demystified”, Power Electronics Technology, June 2006. Alan Elbanhawy, “Effect of Parasitic Inductance on Switching Performance”, Proc. PCIM Europe, pp. 251-255. Alan Elbanhawy, “Mathematical Treatment for HS MOSFET Turn Off”, Proc PEDS 2003. Alan Elbanhawy, “Effect of Parasitic Inductance on Switching Performance of Synchronous Buck Converter”, Proc Intel Technology Symposium 2003. Chris Kocon, Jon Gladish, and Ashok Challa, “Advanced Physics-Based Modeling of Power MOSFET Device Performance in the Synchronous Buck Converter”, Proc. PCIM Europe 2006. Jon Klein, “Shoot-Through in Synchronous Buck Converters”, AN6003, Fairchild Semiconductor. Arthur Black, Jon Gladish, and Young-Sub Jeong, “Practical, Hands-on Lab Experience in Addressing Shoot-Through in Synchronous Buck Regulators”, Proc. PCIM Europe 2006. Intel Corporation, “Energy Star System Implementation”, February 2007 revsion-001.

Jon Gladish is an application engineer at Fairchild Semiconductor responsible for notebook power product development. Prior to Fairchild, Jon worked at Harris Semiconductor (Intersil) as an application engineer focusing on the development of high voltage IGBTs, MCTs and diodes for various AC-DC and DC-DC topologies. Jon’s professional interests include developing high performance MOSFET and multichip modules (MCM) solutions for low voltage DC-DC converters.

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