Transistors and Layout 1
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Topics Basic fabrication steps. Transistor structures. Basic transistor behavior. Latch up.
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Fabrication services
Educational services: – – – –
U.S.: MOSIS EC: EuroPractice Taiwan: CIC Japan: VDEC
Foundry = fabrication line for hire. (A building equipped for the casting of metal or glass, microsoft office dictionary) – Foundries are major source of fab capacity today.
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Wafers
A wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are constructed by doping (for example, diffusion or ion implantation, etching, and deposition of various materials.
Wafers are cut out of silicon boules A boule is a single crystal silicone from which wafers are cut using diamond saws.
http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Fabrication Process
Once the wafers are prepared, many process steps are necessary to produce the desired semiconductor integrated circuit. In general, the steps can be grouped into four areas: •Front end processing (formation of transistors on silicon wafers) •Back end processing (interconnection of transistors by metal wires) •Test •Packaging
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Deposition
Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.
http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Removal or Etching Process
Removal processes are any that remove material from the wafer either in bulk or selective form and consist primarily of etch processes, both wet etching and dry etching such as reactive ion etch (RIE). Chemical mechanical planarization (CMP) is also a removal process used between levels.
http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Masking and Patterning
Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist. The photoresist is exposed by a stepper, a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.
Many modern chips have eight or more levels produced in over 300 sequenced processing steps.
http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Fabrication processes
IC built on silicon substrate (mono crystal silicone): – some structures diffused into substrate; – other structures built on top of substrate.
Substrate regions are doped with n-type and p-type impurities. (n+,p+ = heavily doped) When silicon is doped, n-type impurities (5-valence electron elements such as arsenic) charge silicon atoms with electrons, p-type impurities (3- valence electrons such as boron) charge them with holes Wires made of polycrystalline silicon (poly), and/or multiple layers of aluminum (metal). Silicon dioxide (SiO2) is insulator. (is grown over Si by heating Si in a pure oxygen or water vapor atmosphere)
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Simple cross section SiO2(insulator)
metal3 metal2 metal1
transistor
via
poly n+
Modern VLSI Design 3e: Chapter 2
p+
n+ substrate substrate Copyright 1998, 2002 Prentice Hall PTR
Photolithography Mask patterns are put on wafer using photosensitive material:
A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 12 in (300 mm) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface. http://en.wikipedia.org/wiki/Fabrication_%28semiconductor%29 Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: (Front-end processing) p-tub
n-tub substrate
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Process steps, cont’d. Pattern polysilicon before diffusion regions:
poly p-tub
Modern VLSI Design 3e: Chapter 2
gate oxide
poly p-tub
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Process steps, cont’d Add diffusions, performing self-masking:
poly n+
p-tub
Modern VLSI Design 3e: Chapter 2
poly n+
p+
p-tub
p+
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Process steps, cont’d Start adding metal layers: (Backend processing) metal 1
metal 1 vias
poly n+
p-tub
Modern VLSI Design 3e: Chapter 2
n+
poly p+
n-tub
p+
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Transistor structure n-type transistor:
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
0.25 micron transistor (Bell Labs) gate oxide silicide source/drain poly
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Transistor layout n-type (tubs may vary): L w
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Electrical Transistor Model Vgs: gate to source voltage Vds: drain to source voltage Ids: current flowing between drain and source k’: transconductance > 0 Vt: threshold voltage > 0 for n-type = Vgs - Vt): – Id = 0.5k’ (W/L)(Vgs - Vt) 2 – Id remains constant over changes in Vds – Increases with transconductance, channel width, and decreases with channel length.
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
0.5 m transconductances From a MOSIS process: n-type: – kn’ = 73 A/V2 – Vtn = 0.7 V
p-type: – kp’ = 21 A/V2 – Vtp = -0.8 V
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Current through a transistor (At saturation) Example: Using 0.5 m transconductance parameter of 73 A/V2, threshold voltage of 0.7 volts, and SCMOS rules (http://www.mosis.com/Technical/Designrules/scmos/scmosmain.html) with W 3, L = 2 : Saturation current at Vgs = 2V: Id = 0.5k’(W/L)(Vgs-Vt)2= 93 A Saturation current at Vgs = 5V: Id = 1012 A ~ 1 mA
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Basic transistor parasitics
There are myriad parasitics and parasitics models. The ones considered here are the most widely-encountered parasitics. Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.
Cg
substrate Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Basic transistor parasitics, cont’d Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.
– Cgs = Col W (Col is the unit overlap capacitance per m2, For small channel length, Col might indirectly depend on L.) – Gate/bulk overlap capacitance. Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Latch-up CMOS ICs have built-in undesirable parasitic silicon-controlled rectifiers (SCRs). When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures.
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Silicon Controlled Rectifier(SCR) Tyristor Circuit anode
p
QuickTime™ and a TIFF (Uncompressed) decompressor are needed to see this picture.
FB n
RB
gate
FB
p
n cathode http://en.wikipedia.org/wiki/Thyristor
In normal mode, no current flows over the pnpn path when the middle pn junction is reverse-biased. With the help of a gate pulse voltage, this pn junction can be forced into its breakdown region, making it conduct current. At that point, there will be a path of current from the anode to the cathode with no resistance even after the gate voltage is withdrawn. This is the basis for a high current from VDD to the ground (substrate) in MOS transistors, called the latch up.
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Parasitic SCR
FB Breakdown
V
Reverse voltage breakdown
FB
circuit Modern VLSI Design 3e: Chapter 2
Rs and Rw control the bias voltage on the green diodes
I-V behavior Copyright 1998, 2002 Prentice Hall PTR
Parasitic SCR structure When transistor on the right conducts, it turns on the transistor on the left, and this in turn forces the first transistor to draw more current, establishing a positive feedback loop.
n
p
p p
n
n Solution: connect the n-tub to the VDD
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.
Doping the tub at the point of contact reduces the resistance of contact, and this makes it more difficult for bipolar transistor to turn on.
Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
Tub tie layout
n+ metal (VDD) n-tub
You can learn more about latch up by downloading the article at http://www.fairchildsemi.com/an/AN/AN-339.pdf#search=%22latch%20up%20problem%22 Modern VLSI Design 3e: Chapter 2
Copyright 1998, 2002 Prentice Hall PTR
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